GNU Radio 3.4.2 C++ API
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Defines | |
#define | MAX_EP0_PKTSIZE 64 |
#define | VRT_VENDOR_IN 0xC0 |
#define | VRT_VENDOR_OUT 0x40 |
#define | VRQ_GET_STATUS 0x80 |
#define | GS_TX_UNDERRUN 0 |
#define | GS_RX_OVERRUN 1 |
#define | VRQ_I2C_READ 0x81 |
#define | VRQ_SPI_READ 0x82 |
#define | VRQ_SET_LED 0x01 |
#define | VRQ_FPGA_LOAD 0x02 |
#define | FL_BEGIN 0 |
#define | FL_XFER 1 |
#define | FL_END 2 |
#define | VRQ_FPGA_WRITE_REG 0x03 |
#define | VRQ_FPGA_SET_RESET 0x04 |
#define | VRQ_FPGA_SET_TX_ENABLE 0x05 |
#define | VRQ_FPGA_SET_RX_ENABLE 0x06 |
#define | VRQ_SET_SLEEP_BITS 0x07 |
#define | SLEEP_ADC0 0x01 |
#define | SLEEP_ADC1 0x02 |
#define | SLEEP_DAC0 0x04 |
#define | SLEEP_DAC1 0x08 |
#define | VRQ_I2C_WRITE 0x08 |
#define | VRQ_SPI_WRITE 0x09 |
#define | VRQ_FPGA_SET_TX_RESET 0x0a |
#define | VRQ_FPGA_SET_RX_RESET 0x0b |
#define | USRP_HASH_SLOT_0_ADDR 0xe1e0 |
#define | USRP_HASH_SLOT_1_ADDR 0xe1f0 |
#define FL_BEGIN 0 |
#define FL_END 2 |
#define FL_XFER 1 |
#define GS_RX_OVERRUN 1 |
#define GS_TX_UNDERRUN 0 |
#define MAX_EP0_PKTSIZE 64 |
#define SLEEP_ADC0 0x01 |
#define SLEEP_ADC1 0x02 |
#define SLEEP_DAC0 0x04 |
#define SLEEP_DAC1 0x08 |
#define USRP_HASH_SLOT_0_ADDR 0xe1e0 |
#define USRP_HASH_SLOT_1_ADDR 0xe1f0 |
#define VRQ_FPGA_LOAD 0x02 |
#define VRQ_FPGA_SET_RESET 0x04 |
#define VRQ_FPGA_SET_RX_ENABLE 0x06 |
#define VRQ_FPGA_SET_RX_RESET 0x0b |
#define VRQ_FPGA_SET_TX_ENABLE 0x05 |
#define VRQ_FPGA_SET_TX_RESET 0x0a |
#define VRQ_FPGA_WRITE_REG 0x03 |
#define VRQ_GET_STATUS 0x80 |
#define VRQ_I2C_READ 0x81 |
#define VRQ_I2C_WRITE 0x08 |
#define VRQ_SET_LED 0x01 |
#define VRQ_SET_SLEEP_BITS 0x07 |
#define VRQ_SPI_READ 0x82 |
#define VRQ_SPI_WRITE 0x09 |
#define VRT_VENDOR_IN 0xC0 |
#define VRT_VENDOR_OUT 0x40 |