fpga_regs_standard.h File Reference

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Defines
#define	FR_INTERP_RATE   32
#define	FR_DECIM_RATE   33
#define	FR_RX_FREQ_0   34
#define	FR_RX_FREQ_1   35
#define	FR_RX_FREQ_2   36
#define	FR_RX_FREQ_3   37
#define	FR_RX_MUX   38
#define	FR_TX_MUX   39
#define	FR_TX_A_REFCLK   40
#define	FR_RX_A_REFCLK   41
#define	FR_TX_B_REFCLK   42
#define	FR_RX_B_REFCLK   43
#define	bmFR_REFCLK_EN   0x80
#define	bmFR_REFCLK_DIVISOR_MASK   0x7f
#define	FR_RX_PHASE_0   44
#define	FR_RX_PHASE_1   45
#define	FR_RX_PHASE_2   46
#define	FR_RX_PHASE_3   47
#define	FR_TX_FORMAT   48
#define	bmFR_TX_FORMAT_16_IQ   0
#define	FR_RX_FORMAT   49
#define	bmFR_RX_FORMAT_SHIFT_MASK   (0x0f << 0)
#define	bmFR_RX_FORMAT_SHIFT_SHIFT   0
#define	bmFR_RX_FORMAT_WIDTH_MASK   (0x1f << 4)
#define	bmFR_RX_FORMAT_WIDTH_SHIFT   4
#define	bmFR_RX_FORMAT_WANT_Q   (0x1 << 9)
#define	bmFR_RX_FORMAT_BYPASS_HB   (0x1 << 10)
#define	FR_USER_0   64
#define	FR_USER_1   65
#define	FR_USER_2   66
#define	FR_USER_3   67
#define	FR_USER_4   68
#define	FR_USER_5   69
#define	FR_USER_6   70
#define	FR_USER_7   71
#define	FR_USER_8   72
#define	FR_USER_9   73
#define	FR_USER_10   74
#define	FR_USER_11   75
#define	FR_USER_12   76
#define	FR_USER_13   77
#define	FR_USER_14   78
#define	FR_USER_15   79
#define	FR_USER_16   80
#define	FR_USER_17   81
#define	FR_USER_18   82
#define	FR_USER_19   83
#define	FR_USER_20   84
#define	FR_USER_21   85
#define	FR_USER_22   86
#define	FR_USER_23   87
#define	FR_USER_24   88
#define	FR_USER_25   89
#define	FR_USER_26   90
#define	FR_USER_27   91
#define	FR_USER_28   92
#define	FR_USER_29   93
#define	FR_USER_30   94
#define	FR_USER_31   95
#define	FR_RX_MASTER_SLAVE   64
#define	bitnoFR_RX_SYNC   0
#define	bitnoFR_RX_SYNC_MASTER   1
#define	bitnoFR_RX_SYNC_SLAVE   2
#define	bmFR_RX_SYNC   (1 <<bitnoFR_RX_SYNC)
#define	bmFR_RX_SYNC_MASTER   (1 <<bitnoFR_RX_SYNC_MASTER)
#define	bmFR_RX_SYNC_SLAVE   (1 <<bitnoFR_RX_SYNC_SLAVE)
#define	bitnoFR_RX_SYNC_INPUT_IOPIN   15
#define	bmFR_RX_SYNC_INPUT_IOPIN   (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
#define	bitnoFR_RX_SYNC_OUTPUT_IOPIN   15
#define	bmFR_RX_SYNC_OUTPUT_IOPIN   (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
#define	FR_RB_IO_RX_A_IO_TX_A   1
#define	FR_RB_IO_RX_B_IO_TX_B   2
#define	FR_RB_CAPS   3
#define	bmFR_RB_CAPS_NDDC_MASK   (0x7 << 0)
#define	bmFR_RB_CAPS_NDDC_SHIFT   0
#define	bmFR_RB_CAPS_RX_HAS_HALFBAND   (0x1 << 3)
#define	bmFR_RB_CAPS_NDUC_MASK   (0x7 << 4)
#define	bmFR_RB_CAPS_NDUC_SHIFT   4
#define	bmFR_RB_CAPS_TX_HAS_HALFBAND   (0x1 << 7)

---

Define Documentation

#define bitnoFR_RX_SYNC   0

#define bitnoFR_RX_SYNC_INPUT_IOPIN   15

#define bitnoFR_RX_SYNC_MASTER   1

#define bitnoFR_RX_SYNC_OUTPUT_IOPIN   15

#define bitnoFR_RX_SYNC_SLAVE   2

#define bmFR_RB_CAPS_NDDC_MASK   (0x7 << 0)

#define bmFR_RB_CAPS_NDDC_SHIFT   0

#define bmFR_RB_CAPS_NDUC_MASK   (0x7 << 4)

#define bmFR_RB_CAPS_NDUC_SHIFT   4

#define bmFR_RB_CAPS_RX_HAS_HALFBAND   (0x1 << 3)

#define bmFR_RB_CAPS_TX_HAS_HALFBAND   (0x1 << 7)

#define bmFR_REFCLK_DIVISOR_MASK   0x7f

#define bmFR_REFCLK_EN   0x80

#define bmFR_RX_FORMAT_BYPASS_HB   (0x1 << 10)

#define bmFR_RX_FORMAT_SHIFT_MASK   (0x0f << 0)

#define bmFR_RX_FORMAT_SHIFT_SHIFT   0

#define bmFR_RX_FORMAT_WANT_Q   (0x1 << 9)

#define bmFR_RX_FORMAT_WIDTH_MASK   (0x1f << 4)

#define bmFR_RX_FORMAT_WIDTH_SHIFT   4

#define bmFR_RX_SYNC   (1 <<bitnoFR_RX_SYNC)

#define bmFR_RX_SYNC_INPUT_IOPIN   (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)

#define bmFR_RX_SYNC_MASTER   (1 <<bitnoFR_RX_SYNC_MASTER)

#define bmFR_RX_SYNC_OUTPUT_IOPIN   (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)

#define bmFR_RX_SYNC_SLAVE   (1 <<bitnoFR_RX_SYNC_SLAVE)

#define bmFR_TX_FORMAT_16_IQ   0

#define FR_DECIM_RATE   33

#define FR_INTERP_RATE   32

#define FR_RB_CAPS   3

#define FR_RB_IO_RX_A_IO_TX_A   1

#define FR_RB_IO_RX_B_IO_TX_B   2

#define FR_RX_A_REFCLK   41

#define FR_RX_B_REFCLK   43

#define FR_RX_FORMAT   49

#define FR_RX_FREQ_0   34

#define FR_RX_FREQ_1   35

#define FR_RX_FREQ_2   36

#define FR_RX_FREQ_3   37

#define FR_RX_MASTER_SLAVE   64

#define FR_RX_MUX   38

#define FR_RX_PHASE_0   44

#define FR_RX_PHASE_1   45

#define FR_RX_PHASE_2   46

#define FR_RX_PHASE_3   47

#define FR_TX_A_REFCLK   40

#define FR_TX_B_REFCLK   42

#define FR_TX_FORMAT   48

#define FR_TX_MUX   39

#define FR_USER_0   64

#define FR_USER_1   65

#define FR_USER_10   74

#define FR_USER_11   75

#define FR_USER_12   76

#define FR_USER_13   77

#define FR_USER_14   78

#define FR_USER_15   79

#define FR_USER_16   80

#define FR_USER_17   81

#define FR_USER_18   82

#define FR_USER_19   83

#define FR_USER_2   66

#define FR_USER_20   84

#define FR_USER_21   85

#define FR_USER_22   86

#define FR_USER_23   87

#define FR_USER_24   88

#define FR_USER_25   89

#define FR_USER_26   90

#define FR_USER_27   91

#define FR_USER_28   92

#define FR_USER_29   93

#define FR_USER_3   67

#define FR_USER_30   94

#define FR_USER_31   95

#define FR_USER_4   68

#define FR_USER_5   69

#define FR_USER_6   70

#define FR_USER_7   71

#define FR_USER_8   72

#define FR_USER_9   73