- Generated on Thu Apr 5 2012 00:36:09 for GNU Radio 3.4.2 C++ API by
1.7.4
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GNU Radio 3.4.2 C++ API
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00001 /* -*- c++ -*- */ 00002 /* 00003 * Copyright 2003 Free Software Foundation, Inc. 00004 * 00005 * This file is part of GNU Radio 00006 * 00007 * GNU Radio is free software; you can redistribute it and/or modify 00008 * it under the terms of the GNU General Public License as published by 00009 * the Free Software Foundation; either version 3, or (at your option) 00010 * any later version. 00011 * 00012 * GNU Radio is distributed in the hope that it will be useful, 00013 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 * GNU General Public License for more details. 00016 * 00017 * You should have received a copy of the GNU General Public License 00018 * along with GNU Radio; see the file COPYING. If not, write to 00019 * the Free Software Foundation, Inc., 51 Franklin Street, 00020 * Boston, MA 02110-1301, USA. 00021 */ 00022 00023 /* 00024 //----------------------------------------------------------------------------- 00025 // File: FX2regs.h 00026 // Contents: EZ-USB FX2 register declarations and bit mask definitions. 00027 // 00028 // $Archive: /USB/Target/Inc/fx2regs.h $ 00029 // $Date$ 00030 // $Revision$ 00031 // 00032 // 00033 // Copyright (c) 2000 Cypress Semiconductor, All rights reserved 00034 //----------------------------------------------------------------------------- 00035 */ 00036 00037 00038 #ifndef FX2REGS_H /* Header Sentry */ 00039 #define FX2REGS_H 00040 00041 #define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h 00042 00043 /* 00044 //----------------------------------------------------------------------------- 00045 // FX2 Related Register Assignments 00046 //----------------------------------------------------------------------------- 00047 00048 // The Ez-USB FX2 registers are defined here. We use FX2regs.h for register 00049 // address allocation by using "#define ALLOCATE_EXTERN". 00050 // When using "#define ALLOCATE_EXTERN", you get (for instance): 00051 // xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40; 00052 // Such lines are created from FX2.h by using the preprocessor. 00053 // Incidently, these lines will not generate any space in the resulting hex 00054 // file; they just bind the symbols to the addresses for compilation. 00055 // You just need to put "#define ALLOCATE_EXTERN" in your main program file; 00056 // i.e. fw.c or a stand-alone C source file. 00057 // Without "#define ALLOCATE_EXTERN", you just get the external reference: 00058 // extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40; 00059 // This uses the concatenation operator "##" to insert a comment "//" 00060 // to cut off the end of the line, "_at_ 0x7B40;", which is not wanted. 00061 */ 00062 00063 00064 #ifdef ALLOCATE_EXTERN 00065 #define EXTERN 00066 #define _AT_(a) at a 00067 #else 00068 #define EXTERN extern 00069 #define _AT_ ;/ ## / 00070 #endif 00071 00072 typedef unsigned char BYTE; 00073 typedef unsigned short WORD; 00074 00075 EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; 00076 EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ; 00077 00078 // General Configuration 00079 00080 EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status 00081 EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration 00082 EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments 00083 EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments 00084 EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state 00085 EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint 00086 EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H 00087 EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L 00088 EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2 00089 EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities 00090 EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision 00091 EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control 00092 00093 // Endpoint Configuration 00094 00095 EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration 00096 EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration 00097 EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration 00098 EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration 00099 EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration 00100 EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration 00101 EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration 00102 EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration 00103 EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration 00104 EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration 00105 EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only) 00106 EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only) 00107 EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only) 00108 EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only) 00109 EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only) 00110 EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only) 00111 EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only) 00112 EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only) 00113 EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H 00114 EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L 00115 EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H 00116 EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L 00117 EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H 00118 EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L 00119 EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H 00120 EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L 00121 EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3) 00122 EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3) 00123 EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3) 00124 EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3) 00125 EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End 00126 EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End 00127 00128 // Interrupts 00129 00130 EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable 00131 EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request 00132 EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable 00133 EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request 00134 EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable 00135 EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request 00136 EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable 00137 EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request 00138 EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable 00139 EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request 00140 EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable 00141 EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request 00142 EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables 00143 EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests 00144 EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables 00145 EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests 00146 EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable 00147 EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request 00148 EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables 00149 EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests 00150 EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit 00151 EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0] 00152 EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector 00153 EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector 00154 EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup 00155 00156 // Input/Output 00157 00158 EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration 00159 EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration 00160 EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration 00161 EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status 00162 EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data 00163 EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control 00164 EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access 00165 EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access 00166 00167 #define EXTAUTODAT1 XAUTODAT1 00168 #define EXTAUTODAT2 XAUTODAT2 00169 00170 // USB Control 00171 00172 EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status 00173 EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend 00174 EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity 00175 EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control 00176 EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H 00177 EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L 00178 EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7 00179 EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address 00180 00181 // Endpoints 00182 00183 EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H 00184 EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L 00185 EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count 00186 EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count 00187 EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H 00188 EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L 00189 EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H 00190 EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L 00191 EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H 00192 EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L 00193 EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H 00194 EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L 00195 EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status 00196 EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status 00197 EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status 00198 EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status 00199 EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status 00200 EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status 00201 EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status 00202 EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags 00203 EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags 00204 EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags 00205 EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags 00206 EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H 00207 EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L 00208 EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H 00209 EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L 00210 EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H 00211 EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L 00212 EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H 00213 EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L 00214 EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte 00215 EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte 00216 EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode 00217 EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data 00218 00219 // GPIF 00220 00221 EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector 00222 EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode 00223 EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states 00224 EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive 00225 EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H 00226 EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L 00227 00228 EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3 00229 EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2 00230 EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1 00231 EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0 00232 00233 #define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility 00234 #define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) 00235 #define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility 00236 #define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) 00237 #define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility 00238 #define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) 00239 #define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility 00240 #define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) 00241 00242 // EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High 00243 // EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low 00244 EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select 00245 EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag 00246 EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger 00247 // EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High 00248 // EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low 00249 EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select 00250 EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag 00251 EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger 00252 // EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High 00253 // EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low 00254 EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select 00255 EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag 00256 EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger 00257 // EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High 00258 // EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low 00259 EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select 00260 EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag 00261 EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger 00262 EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only) 00263 EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac 00264 EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger 00265 EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG 00266 EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states 00267 EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles 00268 00269 // UDMA 00270 00271 EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state 00272 EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria 00273 EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state 00274 EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state 00275 EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ; 00276 EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe 00277 EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge 00278 EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe 00279 EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift 00280 EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte 00281 EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte 00282 EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only 00283 00284 00285 // Debug/Test 00286 00287 EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug 00288 EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration 00289 EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes 00290 EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override 00291 EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM 00292 EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals 00293 EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs 00294 00295 // Endpoint Buffers 00296 00297 EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer 00298 EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer 00299 EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer 00300 EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT) 00301 EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT) 00302 EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT) 00303 EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT) 00304 00305 #undef EXTERN 00306 #undef _AT_ 00307 00308 /*----------------------------------------------------------------------------- 00309 Special Function Registers (SFRs) 00310 The byte registers and bits defined in the following list are based 00311 on the Synopsis definition of the 8051 Special Function Registers for EZ-USB. 00312 If you modify the register definitions below, please regenerate the file 00313 "ezregs.inc" which includes the same basic information for assembly inclusion. 00314 -----------------------------------------------------------------------------*/ 00315 00316 sfr at 0x80 IOA; 00317 sfr at 0x81 SP; 00318 sfr at 0x82 DPL; 00319 sfr at 0x83 DPH; 00320 sfr at 0x84 DPL1; 00321 sfr at 0x85 DPH1; 00322 sfr at 0x86 DPS; 00323 /* DPS */ 00324 sbit at 0x86+0 SEL; 00325 sfr at 0x87 PCON; /* PCON */ 00326 //sbit IDLE = 0x87+0; 00327 //sbit STOP = 0x87+1; 00328 //sbit GF0 = 0x87+2; 00329 //sbit GF1 = 0x87+3; 00330 //sbit SMOD0 = 0x87+7; 00331 sfr at 0x88 TCON; 00332 /* TCON */ 00333 sbit at 0x88+0 IT0; 00334 sbit at 0x88+1 IE0; 00335 sbit at 0x88+2 IT1; 00336 sbit at 0x88+3 IE1; 00337 sbit at 0x88+4 TR0; 00338 sbit at 0x88+5 TF0; 00339 sbit at 0x88+6 TR1; 00340 sbit at 0x88+7 TF1; 00341 sfr at 0x89 TMOD; 00342 /* TMOD */ 00343 //sbit M00 = 0x89+0; 00344 //sbit M10 = 0x89+1; 00345 //sbit CT0 = 0x89+2; 00346 //sbit GATE0 = 0x89+3; 00347 //sbit M01 = 0x89+4; 00348 //sbit M11 = 0x89+5; 00349 //sbit CT1 = 0x89+6; 00350 //sbit GATE1 = 0x89+7; 00351 sfr at 0x8A TL0; 00352 sfr at 0x8B TL1; 00353 sfr at 0x8C TH0; 00354 sfr at 0x8D TH1; 00355 sfr at 0x8E CKCON; 00356 /* CKCON */ 00357 //sbit MD0 = 0x89+0; 00358 //sbit MD1 = 0x89+1; 00359 //sbit MD2 = 0x89+2; 00360 //sbit T0M = 0x89+3; 00361 //sbit T1M = 0x89+4; 00362 //sbit T2M = 0x89+5; 00363 // sfr at 0x8F SPC_FNC; // Was WRS in Reg320 00364 /* CKCON */ 00365 //sbit WRS = 0x8F+0; 00366 sfr at 0x90 IOB; 00367 sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320 00368 /* EXIF */ 00369 //sbit USBINT = 0x91+4; 00370 //sbit I2CINT = 0x91+5; 00371 //sbit IE4 = 0x91+6; 00372 //sbit IE5 = 0x91+7; 00373 sfr at 0x92 MPAGE; 00374 sfr at 0x98 SCON0; 00375 /* SCON0 */ 00376 sbit at 0x98+0 RI; 00377 sbit at 0x98+1 TI; 00378 sbit at 0x98+2 RB8; 00379 sbit at 0x98+3 TB8; 00380 sbit at 0x98+4 REN; 00381 sbit at 0x98+5 SM2; 00382 sbit at 0x98+6 SM1; 00383 sbit at 0x98+7 SM0; 00384 sfr at 0x99 SBUF0; 00385 00386 sfr at 0x9A APTR1H; 00387 sfr at 0x9B APTR1L; 00388 sfr at 0x9C AUTODAT1; 00389 sfr at 0x9D AUTOPTRH2; 00390 sfr at 0x9E AUTOPTRL2; 00391 sfr at 0x9F AUTODAT2; 00392 sfr at 0xA0 IOC; 00393 sfr at 0xA1 INT2CLR; 00394 sfr at 0xA2 INT4CLR; 00395 00396 #define AUTOPTRH1 APTR1H 00397 #define AUTOPTRL1 APTR1L 00398 00399 sfr at 0xA8 IE; 00400 /* IE */ 00401 sbit at 0xA8+0 EX0; 00402 sbit at 0xA8+1 ET0; 00403 sbit at 0xA8+2 EX1; 00404 sbit at 0xA8+3 ET1; 00405 sbit at 0xA8+4 ES0; 00406 sbit at 0xA8+5 ET2; 00407 sbit at 0xA8+6 ES1; 00408 sbit at 0xA8+7 EA; 00409 00410 sfr at 0xAA EP2468STAT; 00411 /* EP2468STAT */ 00412 //sbit EP2E = 0xAA+0; 00413 //sbit EP2F = 0xAA+1; 00414 //sbit EP4E = 0xAA+2; 00415 //sbit EP4F = 0xAA+3; 00416 //sbit EP6E = 0xAA+4; 00417 //sbit EP6F = 0xAA+5; 00418 //sbit EP8E = 0xAA+6; 00419 //sbit EP8F = 0xAA+7; 00420 00421 sfr at 0xAB EP24FIFOFLGS; 00422 sfr at 0xAC EP68FIFOFLGS; 00423 sfr at 0xAF AUTOPTRSETUP; 00424 /* AUTOPTRSETUP */ 00425 // sbit EXTACC = 0xAF+0; 00426 // sbit APTR1FZ = 0xAF+1; 00427 // sbit APTR2FZ = 0xAF+2; 00428 00429 sfr at 0xB0 IOD; 00430 sfr at 0xB1 IOE; 00431 sfr at 0xB2 OEA; 00432 sfr at 0xB3 OEB; 00433 sfr at 0xB4 OEC; 00434 sfr at 0xB5 OED; 00435 sfr at 0xB6 OEE; 00436 00437 sfr at 0xB8 IP; 00438 /* IP */ 00439 sbit at 0xB8+0 PX0; 00440 sbit at 0xB8+1 PT0; 00441 sbit at 0xB8+2 PX1; 00442 sbit at 0xB8+3 PT1; 00443 sbit at 0xB8+4 PS0; 00444 sbit at 0xB8+5 PT2; 00445 sbit at 0xB8+6 PS1; 00446 00447 sfr at 0xBA EP01STAT; 00448 sfr at 0xBB GPIFTRIG; 00449 00450 sfr at 0xBD GPIFSGLDATH; 00451 sfr at 0xBE GPIFSGLDATLX; 00452 sfr at 0xBF GPIFSGLDATLNOX; 00453 00454 sfr at 0xC0 SCON1; 00455 /* SCON1 */ 00456 sbit at 0xC0+0 RI1; 00457 sbit at 0xC0+1 TI1; 00458 sbit at 0xC0+2 RB81; 00459 sbit at 0xC0+3 TB81; 00460 sbit at 0xC0+4 REN1; 00461 sbit at 0xC0+5 SM21; 00462 sbit at 0xC0+6 SM11; 00463 sbit at 0xC0+7 SM01; 00464 sfr at 0xC1 SBUF1; 00465 sfr at 0xC8 T2CON; 00466 /* T2CON */ 00467 sbit at 0xC8+0 CP_RL2; 00468 sbit at 0xC8+1 C_T2; 00469 sbit at 0xC8+2 TR2; 00470 sbit at 0xC8+3 EXEN2; 00471 sbit at 0xC8+4 TCLK; 00472 sbit at 0xC8+5 RCLK; 00473 sbit at 0xC8+6 EXF2; 00474 sbit at 0xC8+7 TF2; 00475 sfr at 0xCA RCAP2L; 00476 sfr at 0xCB RCAP2H; 00477 sfr at 0xCC TL2; 00478 sfr at 0xCD TH2; 00479 sfr at 0xD0 PSW; 00480 /* PSW */ 00481 sbit at 0xD0+0 P; 00482 sbit at 0xD0+1 FL; 00483 sbit at 0xD0+2 OV; 00484 sbit at 0xD0+3 RS0; 00485 sbit at 0xD0+4 RS1; 00486 sbit at 0xD0+5 F0; 00487 sbit at 0xD0+6 AC; 00488 sbit at 0xD0+7 CY; 00489 sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 00490 /* EICON */ 00491 sbit at 0xD8+3 INT6; 00492 sbit at 0xD8+4 RESI; 00493 sbit at 0xD8+5 ERESI; 00494 sbit at 0xD8+7 SMOD1; 00495 sfr at 0xE0 ACC; 00496 sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320 00497 /* EIE */ 00498 sbit at 0xE8+0 EIUSB; 00499 sbit at 0xE8+1 EI2C; 00500 sbit at 0xE8+2 EIEX4; 00501 sbit at 0xE8+3 EIEX5; 00502 sbit at 0xE8+4 EIEX6; 00503 sfr at 0xF0 B; 00504 sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 00505 /* EIP */ 00506 sbit at 0xF8+0 PUSB; 00507 sbit at 0xF8+1 PI2C; 00508 sbit at 0xF8+2 EIPX4; 00509 sbit at 0xF8+3 EIPX5; 00510 sbit at 0xF8+4 EIPX6; 00511 00512 /*----------------------------------------------------------------------------- 00513 Bit Masks 00514 -----------------------------------------------------------------------------*/ 00515 00516 #define bmBIT0 1 00517 #define bmBIT1 2 00518 #define bmBIT2 4 00519 #define bmBIT3 8 00520 #define bmBIT4 16 00521 #define bmBIT5 32 00522 #define bmBIT6 64 00523 #define bmBIT7 128 00524 00525 /* CPU Control & Status Register (CPUCS) */ 00526 #define bmPRTCSTB bmBIT5 00527 #define bmCLKSPD (bmBIT4 | bmBIT3) 00528 #define bmCLKSPD1 bmBIT4 00529 #define bmCLKSPD0 bmBIT3 00530 #define bmCLKINV bmBIT2 00531 #define bmCLKOE bmBIT1 00532 #define bm8051RES bmBIT0 00533 /* Port Alternate Configuration Registers */ 00534 /* Port A (PORTACFG) */ 00535 #define bmFLAGD bmBIT7 00536 #define bmINT1 bmBIT1 00537 #define bmINT0 bmBIT0 00538 /* Port C (PORTCCFG) */ 00539 #define bmGPIFA7 bmBIT7 00540 #define bmGPIFA6 bmBIT6 00541 #define bmGPIFA5 bmBIT5 00542 #define bmGPIFA4 bmBIT4 00543 #define bmGPIFA3 bmBIT3 00544 #define bmGPIFA2 bmBIT2 00545 #define bmGPIFA1 bmBIT1 00546 #define bmGPIFA0 bmBIT0 00547 /* Port E (PORTECFG) */ 00548 #define bmGPIFA8 bmBIT7 00549 #define bmT2EX bmBIT6 00550 #define bmINT6 bmBIT5 00551 #define bmRXD1OUT bmBIT4 00552 #define bmRXD0OUT bmBIT3 00553 #define bmT2OUT bmBIT2 00554 #define bmT1OUT bmBIT1 00555 #define bmT0OUT bmBIT0 00556 00557 /* I2C Control & Status Register (I2CS) */ 00558 #define bmSTART bmBIT7 00559 #define bmSTOP bmBIT6 00560 #define bmLASTRD bmBIT5 00561 #define bmID (bmBIT4 | bmBIT3) 00562 #define bmBERR bmBIT2 00563 #define bmACK bmBIT1 00564 #define bmDONE bmBIT0 00565 /* I2C Control Register (I2CTL) */ 00566 #define bmSTOPIE bmBIT1 00567 #define bm400KHZ bmBIT0 00568 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */ 00569 #define bmIV4 bmBIT6 00570 #define bmIV3 bmBIT5 00571 #define bmIV2 bmBIT4 00572 #define bmIV1 bmBIT3 00573 #define bmIV0 bmBIT2 00574 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */ 00575 #define bmEP0ACK bmBIT6 00576 #define bmHSGRANT bmBIT5 00577 #define bmURES bmBIT4 00578 #define bmSUSP bmBIT3 00579 #define bmSUTOK bmBIT2 00580 #define bmSOF bmBIT1 00581 #define bmSUDAV bmBIT0 00582 /* Breakpoint register (BREAKPT) */ 00583 #define bmBREAK bmBIT3 00584 #define bmBPPULSE bmBIT2 00585 #define bmBPEN bmBIT1 00586 /* Interrupt 2 & 4 Setup (INTSETUP) */ 00587 #define bmAV2EN bmBIT3 00588 #define bmINT4IN bmBIT1 00589 #define bmAV4EN bmBIT0 00590 /* USB Control & Status Register (USBCS) */ 00591 #define bmHSM bmBIT7 00592 #define bmDISCON bmBIT3 00593 #define bmNOSYNSOF bmBIT2 00594 #define bmRENUM bmBIT1 00595 #define bmSIGRESUME bmBIT0 00596 /* Wakeup Control and Status Register (WAKEUPCS) */ 00597 #define bmWU2 bmBIT7 00598 #define bmWU bmBIT6 00599 #define bmWU2POL bmBIT5 00600 #define bmWUPOL bmBIT4 00601 #define bmDPEN bmBIT2 00602 #define bmWU2EN bmBIT1 00603 #define bmWUEN bmBIT0 00604 /* End Point 0 Control & Status Register (EP0CS) */ 00605 #define bmHSNAK bmBIT7 00606 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */ 00607 #define bmEPBUSY bmBIT1 00608 #define bmEPSTALL bmBIT0 00609 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */ 00610 #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) 00611 #define bmEPFULL bmBIT3 00612 #define bmEPEMPTY bmBIT2 00613 /* Endpoint Status (EP2468STAT) SFR bits */ 00614 #define bmEP8FULL bmBIT7 00615 #define bmEP8EMPTY bmBIT6 00616 #define bmEP6FULL bmBIT5 00617 #define bmEP6EMPTY bmBIT4 00618 #define bmEP4FULL bmBIT3 00619 #define bmEP4EMPTY bmBIT2 00620 #define bmEP2FULL bmBIT1 00621 #define bmEP2EMPTY bmBIT0 00622 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */ 00623 #define bmSDPAUTO bmBIT0 00624 /* Endpoint Data Toggle Control (TOGCTL) */ 00625 #define bmQUERYTOGGLE bmBIT7 00626 #define bmSETTOGGLE bmBIT6 00627 #define bmRESETTOGGLE bmBIT5 00628 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 00629 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */ 00630 #define bmEP8IBN bmBIT5 00631 #define bmEP6IBN bmBIT4 00632 #define bmEP4IBN bmBIT3 00633 #define bmEP2IBN bmBIT2 00634 #define bmEP1IBN bmBIT1 00635 #define bmEP0IBN bmBIT0 00636 00637 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */ 00638 #define bmEP8PING bmBIT7 00639 #define bmEP6PING bmBIT6 00640 #define bmEP4PING bmBIT5 00641 #define bmEP2PING bmBIT4 00642 #define bmEP1PING bmBIT3 00643 #define bmEP0PING bmBIT2 00644 #define bmIBN bmBIT0 00645 00646 /* Interface Configuration bits (IFCONFIG) */ 00647 #define bmIFCLKSRC bmBIT7 // set == INTERNAL 00648 #define bm3048MHZ bmBIT6 // set == 48 MHz 00649 #define bmIFCLKOE bmBIT5 00650 #define bmIFCLKPOL bmBIT4 00651 #define bmASYNC bmBIT3 00652 #define bmGSTATE bmBIT2 00653 #define bmIFCFG1 bmBIT1 00654 #define bmIFCFG0 bmBIT0 00655 #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) 00656 #define bmIFGPIF bmIFCFG1 00657 00658 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */ 00659 #define bmINFM bmBIT6 00660 #define bmOEP bmBIT5 00661 #define bmAUTOOUT bmBIT4 00662 #define bmAUTOIN bmBIT3 00663 #define bmZEROLENIN bmBIT2 00664 // must be zero bmBIT1 00665 #define bmWORDWIDE bmBIT0 00666 00667 /* 00668 * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features 00669 */ 00670 #define bmNOAUTOARM bmBIT1 // these don't match the docs 00671 #define bmSKIPCOMMIT bmBIT0 // these don't match the docs 00672 00673 #define bmDYN_OUT bmBIT1 // these do... 00674 #define bmENH_PKT bmBIT0 00675 00676 00677 /* Fifo Reset bits (FIFORESET) */ 00678 #define bmNAKALL bmBIT7 00679 00680 /* Endpoint Configuration (EPxCFG) */ 00681 #define bmVALID bmBIT7 00682 #define bmIN bmBIT6 00683 #define bmTYPE1 bmBIT5 00684 #define bmTYPE0 bmBIT4 00685 #define bmISOCHRONOUS bmTYPE0 00686 #define bmBULK bmTYPE1 00687 #define bmINTERRUPT (bmTYPE1 | bmTYPE0) 00688 #define bm1KBUF bmBIT3 00689 #define bmBUF1 bmBIT1 00690 #define bmBUF0 bmBIT0 00691 #define bmQUADBUF 0 00692 #define bmINVALIDBUF bmBUF0 00693 #define bmDOUBLEBUF bmBUF1 00694 #define bmTRIPLEBUF (bmBUF1 | bmBUF0) 00695 00696 /* OUTPKTEND */ 00697 #define bmSKIP bmBIT7 // low 4 bits specify which end point 00698 00699 /* GPIFTRIG defs */ 00700 #define bmGPIF_IDLE bmBIT7 // status bit 00701 00702 #define bmGPIF_EP2_START 0 00703 #define bmGPIF_EP4_START 1 00704 #define bmGPIF_EP6_START 2 00705 #define bmGPIF_EP8_START 3 00706 #define bmGPIF_READ bmBIT2 00707 #define bmGPIF_WRITE 0 00708 00709 /* EXIF bits */ 00710 #define bmEXIF_USBINT bmBIT4 00711 #define bmEXIF_I2CINT bmBIT5 00712 #define bmEXIF_IE4 bmBIT6 00713 #define bmEXIF_IE5 bmBIT7 00714 00715 00716 #endif /* FX2REGS_H */
1.7.4