GNU Radio 3.4.2 C++ API
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00001 /* 00002 * USRP - Universal Software Radio Peripheral 00003 * 00004 * Copyright (C) 2003,2004 Free Software Foundation, Inc. 00005 * 00006 * This program is free software; you can redistribute it and/or modify 00007 * it under the terms of the GNU General Public License as published by 00008 * the Free Software Foundation; either version 3 of the License, or 00009 * (at your option) any later version. 00010 * 00011 * This program is distributed in the hope that it will be useful, 00012 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 * GNU General Public License for more details. 00015 * 00016 * You should have received a copy of the GNU General Public License 00017 * along with this program; if not, write to the Free Software 00018 * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 00019 */ 00020 00021 #ifndef INCLUDED_FPGA_REV1_H 00022 #define INCLUDED_FPGA_REV1_H 00023 00024 void fpga_set_reset (unsigned char v); 00025 void fpga_set_tx_enable (unsigned char v); 00026 void fpga_set_rx_enable (unsigned char v); 00027 void fpga_set_tx_reset (unsigned char v); 00028 void fpga_set_rx_reset (unsigned char v); 00029 00030 unsigned char fpga_has_room_for_packet (void); 00031 unsigned char fpga_has_packet_avail (void); 00032 00033 #if (UC_BOARD_HAS_FPGA) 00034 /* 00035 * return TRUE iff FPGA internal fifo has room for 512 bytes. 00036 */ 00037 #define fpga_has_room_for_packet() (GPIFREADYSTAT & bmFPGA_HAS_SPACE) 00038 00039 /* 00040 * return TRUE iff FPGA internal fifo has at least 512 bytes available. 00041 */ 00042 #define fpga_has_packet_avail() (GPIFREADYSTAT & bmFPGA_PKT_AVAIL) 00043 00044 #else /* no FPGA on board. fake it. */ 00045 00046 #define fpga_has_room_for_packet() TRUE 00047 #define fpga_has_packet_avail() TRUE 00048 00049 #endif 00050 00051 #define fpga_clear_flags() \ 00052 do { \ 00053 USRP_PE |= bmPE_FPGA_CLR_STATUS; \ 00054 USRP_PE &= ~bmPE_FPGA_CLR_STATUS; \ 00055 } while (0) 00056 00057 00058 #endif /* INCLUDED_FPGA_REV1_H */