diff options
Diffstat (limited to 'usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf')
| -rw-r--r-- | usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 8296a453e0..6b4764078a 100644 --- a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -372,11 +372,16 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v @@ -412,4 +417,6 @@ set_global_assignment -name VERILOG_FILE usrp_inband_usb.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
\ No newline at end of file |