diff options
Diffstat (limited to 'gr-sounder/src/fpga/top/usrp_sounder.qsf')
| -rw-r--r--[-rwxr-xr-x] | gr-sounder/src/fpga/top/usrp_sounder.qsf | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qsf b/gr-sounder/src/fpga/top/usrp_sounder.qsf index 5ff52583f3..4d60f5f13f 100755..100644 --- a/gr-sounder/src/fpga/top/usrp_sounder.qsf +++ b/gr-sounder/src/fpga/top/usrp_sounder.qsf @@ -236,7 +236,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
@@ -368,13 +368,15 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name VERILOG_FILE ../lib/strobe.v
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC
set_global_assignment -name VERILOG_FILE ../lib/lfsr_constants.v
set_global_assignment -name VERILOG_FILE ../lib/lfsr.v
set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
set_global_assignment -name VERILOG_FILE ../lib/dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/sounder_rx.v
set_global_assignment -name VERILOG_FILE ../lib/sounder_tx.v
+set_global_assignment -name VERILOG_FILE ../lib/sounder_ctrl.v
set_global_assignment -name VERILOG_FILE ../lib/sounder.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v
@@ -390,4 +392,5 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_co set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sounder.v
\ No newline at end of file +set_global_assignment -name VERILOG_FILE usrp_sounder.v
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file |