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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/sdr_lib/add2_and_round.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/sdr_lib/add2_and_round.v')
| -rw-r--r-- | usrp2/fpga/sdr_lib/add2_and_round.v | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/usrp2/fpga/sdr_lib/add2_and_round.v b/usrp2/fpga/sdr_lib/add2_and_round.v deleted file mode 100644 index 146af28dae..0000000000 --- a/usrp2/fpga/sdr_lib/add2_and_round.v +++ /dev/null @@ -1,11 +0,0 @@ - -module add2_and_round - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]); - -endmodule // add2_and_round |