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authorMatt Ettus <matt@ettus.com>2009-09-02 21:27:18 -0700
committerMatt Ettus <matt@ettus.com>2009-09-02 21:27:18 -0700
commit77dc1a9ba4ce9940d974edef8711d3eba85c0608 (patch)
treed5334277a7342ce832952e0a2f2fc209867a0269 /usrp2/fpga/control_lib
parent3113a7bbf56462cde4a6be4a15d5f8296e37ae8a (diff)
bring the testbench files up to date
Diffstat (limited to 'usrp2/fpga/control_lib')
-rw-r--r--usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v b/usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v
index 8d8a479540..5ce726977c 100644
--- a/usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v
@@ -17,7 +17,7 @@ module fifo_2clock_cascade
.dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
.space(s1_space), .occupied(s1_occupied) );
- fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+ fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
(.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
.rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
.arst(arst) );