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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/control_lib/wb_ram_dist.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/control_lib/wb_ram_dist.v')
| -rw-r--r-- | usrp2/fpga/control_lib/wb_ram_dist.v | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/usrp2/fpga/control_lib/wb_ram_dist.v b/usrp2/fpga/control_lib/wb_ram_dist.v deleted file mode 100644 index cffc2f4237..0000000000 --- a/usrp2/fpga/control_lib/wb_ram_dist.v +++ /dev/null @@ -1,33 +0,0 @@ - - -module wb_ram_dist - #(parameter AWIDTH=8) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - input [3:0] sel_i, - output [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i & sel_i[3]) - distram[adr_i][31:24] <= dat_i[31:24]; - if(stb_i & we_i & sel_i[2]) - distram[adr_i][24:16] <= dat_i[24:16]; - if(stb_i & we_i & sel_i[1]) - distram[adr_i][15:8] <= dat_i[15:8]; - if(stb_i & we_i & sel_i[0]) - distram[adr_i][7:0] <= dat_i[7:0]; - end // always @ (posedge clk_i) - - assign dat_o = distram[adr_i]; - assign ack_o = stb_i; - -endmodule // wb_ram_dist - - |