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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/control_lib/setting_reg.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/control_lib/setting_reg.v')
| -rw-r--r-- | usrp2/fpga/control_lib/setting_reg.v | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/usrp2/fpga/control_lib/setting_reg.v b/usrp2/fpga/control_lib/setting_reg.v deleted file mode 100644 index ccbaa3d2e3..0000000000 --- a/usrp2/fpga/control_lib/setting_reg.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module setting_reg - #(parameter my_addr = 0) - (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); - - always @(posedge clk) - if(rst) - begin - out <= 32'd0; - changed <= 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= in; - changed <= 1'b1; - end - else - changed <= 1'b0; - -endmodule // setting_reg |