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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/control_lib/gray_send.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/control_lib/gray_send.v')
| -rw-r--r-- | usrp2/fpga/control_lib/gray_send.v | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/usrp2/fpga/control_lib/gray_send.v b/usrp2/fpga/control_lib/gray_send.v deleted file mode 100644 index 7fc07d40c4..0000000000 --- a/usrp2/fpga/control_lib/gray_send.v +++ /dev/null @@ -1,29 +0,0 @@ - - - -module gray_send - #(parameter WIDTH = 8) - (input clk_in, input [WIDTH-1:0] addr_in, - input clk_out, output reg [WIDTH-1:0] addr_out); - - reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; - wire [WIDTH-1:0] gray, bin; - - bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); - - always @(posedge clk_in) - gray_clkin <= gray; - - always @(posedge clk_out) - gray_clkout <= gray_clkin; - - always @(posedge clk_out) - gray_clkout_d1 <= gray_clkout; - - gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); - - // FIXME we may not need the next register, but it may help timing - always @(posedge clk_out) - addr_out <= bin; - -endmodule // gray_send |