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| author | Tom <trondeau@vt.edu> | 2009-10-06 10:40:39 -0700 |
|---|---|---|
| committer | Tom <trondeau@vt.edu> | 2009-10-06 10:40:39 -0700 |
| commit | bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef (patch) | |
| tree | dbf63fb638238e389ad970f2f4443299491e8fc6 /usrp2/fpga/control_lib/fifo_reader.v | |
| parent | 314726ae7457b37f442a2751285b75b0d616c0f4 (diff) | |
| parent | 3f8026a00c261c788357b3a04f5b338a6cda4d0e (diff) | |
Merge branch 'master' into sync
Conflicts:
gr-utils/src/python/gr_plot_qt.py
gr-utils/src/python/pyqt_plot.py
gr-utils/src/python/pyqt_plot.ui
Diffstat (limited to 'usrp2/fpga/control_lib/fifo_reader.v')
| -rw-r--r-- | usrp2/fpga/control_lib/fifo_reader.v | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/usrp2/fpga/control_lib/fifo_reader.v b/usrp2/fpga/control_lib/fifo_reader.v deleted file mode 100644 index 49d05b1a63..0000000000 --- a/usrp2/fpga/control_lib/fifo_reader.v +++ /dev/null @@ -1,28 +0,0 @@ - -module fifo_reader - #(parameter rate=4) - (input clk, - input [31:0] data_in, - output read_o - input ready_i, - input done_i - ); - - reg [7:0] state = 0; - - always @(posedge clk) - if(ready) - if(state == rate) - state <= 0; - else - state <= state + 1; - else - state <= 0; - - assign read = (state == rate); - - initial $monitor(data_in); - -endmodule // fifo_reader - - |