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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/control_lib/clock_control_tb.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/control_lib/clock_control_tb.v')
| -rw-r--r-- | usrp2/fpga/control_lib/clock_control_tb.v | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/usrp2/fpga/control_lib/clock_control_tb.v b/usrp2/fpga/control_lib/clock_control_tb.v deleted file mode 100644 index 4e705cf23e..0000000000 --- a/usrp2/fpga/control_lib/clock_control_tb.v +++ /dev/null @@ -1,35 +0,0 @@ - - -module clock_control_tb(); - - clock_control clock_control - (.reset(reset), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .clk_en(clk_en), - .clk_sel(clk_sel), - .clk_func(clk_func), - .clk_status(clk_status), - - .sen(sen), - .sclk(sclk), - .sdi(sdi), - .sdo(sdo) - ); - - reg reset, aux_clk; - - wire [1:0] clk_sel, clk_en; - - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial aux_clk = 1'b0; - always #10 aux_clk = ~aux_clk; - - initial $dumpfile("clock_control_tb.vcd"); - initial $dumpvars(0,clock_control_tb); - - initial #10000 $finish; - -endmodule // clock_control_tb |