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authoreb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-01-17 22:44:13 +0000
committereb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-01-17 22:44:13 +0000
commit4b5e1238492fe40727d19abefe22ae448c720419 (patch)
tree5e351e65a1dbe006734145f34a1bb8d18981115f /usrp/fpga/sdr_lib/tx_buffer.v
parent01eb527e0c1f445fab7c7cef039ba623e93f8c7c (diff)
Applied patch from Brett Trotter that stuffs zeros into the head of
the tx signal processing pipeline when the Tx FIFO is empty. This results in the DACs outputing zeros when there's no data, unless the tx pipeline is disabled on the host. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/sdr_lib/tx_buffer.v')
-rw-r--r--usrp/fpga/sdr_lib/tx_buffer.v20
1 files changed, 10 insertions, 10 deletions
diff --git a/usrp/fpga/sdr_lib/tx_buffer.v b/usrp/fpga/sdr_lib/tx_buffer.v
index ff8fd839dc..63202c9df9 100644
--- a/usrp/fpga/sdr_lib/tx_buffer.v
+++ b/usrp/fpga/sdr_lib/tx_buffer.v
@@ -66,20 +66,20 @@ module tx_buffer
load_next <= #1 4'd0;
end
else
- if((load_next != channels) & !tx_empty)
+ if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
- 4'd0 : tx_i_0 <= #1 fifodata;
- 4'd1 : tx_q_0 <= #1 fifodata;
- 4'd2 : tx_i_1 <= #1 fifodata;
- 4'd3 : tx_q_1 <= #1 fifodata;
- 4'd4 : tx_i_2 <= #1 fifodata;
- 4'd5 : tx_q_2 <= #1 fifodata;
- 4'd6 : tx_i_3 <= #1 fifodata;
- 4'd7 : tx_q_3 <= #1 fifodata;
+ 4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
+ 4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
- end // if ((load_next != channels) & !tx_empty)
+ end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;