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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp/fpga/models/fifo.v | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp/fpga/models/fifo.v')
| -rw-r--r-- | usrp/fpga/models/fifo.v | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/usrp/fpga/models/fifo.v b/usrp/fpga/models/fifo.v deleted file mode 100644 index 0ade49e9c8..0000000000 --- a/usrp/fpga/models/fifo.v +++ /dev/null @@ -1,82 +0,0 @@ -// Model of FIFO in Altera - -module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, - rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); - - parameter width = 16; - parameter depth = 1024; - parameter addr_bits = 10; - - //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req - - input [width-1:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [width-1:0] q; - output rdfull; - output rdempty; - output reg [addr_bits-1:0] rdusedw; - output wrfull; - output wrempty; - output reg [addr_bits-1:0] wrusedw; - - reg [width-1:0] mem [0:depth-1]; - reg [addr_bits-1:0] rdptr; - reg [addr_bits-1:0] wrptr; - -`ifdef rd_req - reg [width-1:0] q; -`else - wire [width-1:0] q; -`endif - - integer i; - - always @( aclr) - begin - wrptr <= #1 0; - rdptr <= #1 0; - for(i=0;i<depth;i=i+1) - mem[i] <= #1 0; - end - - always @(posedge wrclk) - if(wrreq) - begin - wrptr <= #1 wrptr+1; - mem[wrptr] <= #1 data; - end - - always @(posedge rdclk) - if(rdreq) - begin - rdptr <= #1 rdptr+1; -`ifdef rd_req - q <= #1 mem[rdptr]; -`endif - end - -`ifdef rd_req -`else - assign q = mem[rdptr]; -`endif - - // Fix these - always @(posedge wrclk) - wrusedw <= #1 wrptr - rdptr; - - always @(posedge rdclk) - rdusedw <= #1 wrptr - rdptr; - - assign wrempty = (wrusedw == 0); - assign wrfull = (wrusedw == depth-1); - - assign rdempty = (rdusedw == 0); - assign rdfull = (rdusedw == depth-1); - -endmodule // fifo - - |