diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-04-16 21:30:13 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-04-16 21:30:13 +0000 |
| commit | 9e04f8e3bfe584f87c4e4f5cc40781ae6a217f00 (patch) | |
| tree | 2ac8c45795006e2664dd96049c2c4cef5d846190 /usrp/firmware/include/fpga_regs_common.h | |
| parent | 36c0ba64703776f4cc2a77adc00740b05e0b055d (diff) | |
Adds capability to independently delay the Auto T/R switching signal
by a configurable number of clock ticks, to allow users to precisely
align their T/R output with the pipeline delays in the transmitter.
There are two new registers:
FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)
...and the corresponding db_base.py methods to set them:
db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)
These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:
subdev.set_atr_tx_delay(...)
...where 'subdev' represents the daughtercard object you're working with.
The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/firmware/include/fpga_regs_common.h')
| -rw-r--r-- | usrp/firmware/include/fpga_regs_common.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/usrp/firmware/include/fpga_regs_common.h b/usrp/firmware/include/fpga_regs_common.h index fe0c81f578..af88900f0d 100644 --- a/usrp/firmware/include/fpga_regs_common.h +++ b/usrp/firmware/include/fpga_regs_common.h @@ -32,8 +32,7 @@ #define FR_TX_SAMPLE_RATE_DIV 0 #define FR_RX_SAMPLE_RATE_DIV 1 -// 2 is available. -// 3 is available. +// 2 and 3 are defined in the ATR section #define FR_MASTER_CTRL 4 // master enable and reset controls # define bmFR_MC_ENABLE_TX (1 << 0) @@ -144,4 +143,8 @@ #define FR_ATR_TXVAL_3 30 #define FR_ATR_RXVAL_3 31 +// Clock ticks to delay rising and falling edge of T/R signal +#define FR_ATR_TX_DELAY 2 +#define FR_ATR_RX_DELAY 3 + #endif /* INCLUDED_FPGA_REGS_COMMON_H */ |