diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-12-27 21:09:26 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-12-27 21:09:26 +0000 |
| commit | 297479844e3d9a6eea54fa69147e6a20c0bfc412 (patch) | |
| tree | 786591a2e3c8aa77d8149630a6a5d00974585af7 /gr-usrp2/src | |
| parent | a09700c26a39ebddbeb56b5ecddedf50f0cc7ac4 (diff) | |
Implements USRP2 peek() command, allowing arbitrary reads from the internal
Wishbone bus. Minor fix for USRP2 sync_to_pps() (uses correct packet type.)
Example:
>>> from gnuradio import usrp2
>>> u = usrp2.source_32fc()
>>> u.peek(0x1234, 4) # Read four bytes at offset 0x1234 (code)
(185, 244, 253, 164)
>>>
The return value will be zero length upon error.
The read address must be 32-bit aligned, and only the lower 16 bits are
significant. The length must be an integral multiple of 4 bytes. There is
currently a read limit of 176 bytes per read; to change requires some additional
firmware changes to allocate a larger reply packet.
WARNING: Trying to read from memory locations not serviced by RAM or by a
Wishbone peripheral may result in a hang requiring a USRP2 power cycle. The
USRP2 internal memory map is documented in usrp2/firmware/lib/memory_map.h.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10172 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'gr-usrp2/src')
| -rw-r--r-- | gr-usrp2/src/usrp2.i | 4 | ||||
| -rw-r--r-- | gr-usrp2/src/usrp2_base.cc | 6 | ||||
| -rw-r--r-- | gr-usrp2/src/usrp2_base.h | 6 |
3 files changed, 16 insertions, 0 deletions
diff --git a/gr-usrp2/src/usrp2.i b/gr-usrp2/src/usrp2.i index df07ee8f4a..a484397f8e 100644 --- a/gr-usrp2/src/usrp2.i +++ b/gr-usrp2/src/usrp2.i @@ -24,6 +24,7 @@ %include "exception.i" %import "gnuradio.i" // the common stuff +%import <stdint.i> %{ #include <gnuradio_swig_bug_workaround.h> @@ -35,6 +36,8 @@ %include <usrp2/tune_result.h> +%template(uint8_t_vector) std::vector<uint8_t>; + // ---------------------------------------------------------------- class usrp2_base : public gr_sync_block @@ -49,6 +52,7 @@ public: %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq; bool fpga_master_clock_freq(long *freq); bool sync_to_pps(); + std::vector<uint8_t> peek(uint32_t addr, uint32_t len); }; // ---------------------------------------------------------------- diff --git a/gr-usrp2/src/usrp2_base.cc b/gr-usrp2/src/usrp2_base.cc index 8f80a0119d..443d1faaa3 100644 --- a/gr-usrp2/src/usrp2_base.cc +++ b/gr-usrp2/src/usrp2_base.cc @@ -67,6 +67,12 @@ usrp2_base::sync_to_pps() return d_u2->sync_to_pps(); } +std::vector<uint8_t> +usrp2_base::peek(uint32_t addr, uint32_t len) +{ + return d_u2->peek(addr, len); +} + bool usrp2_base::start() { diff --git a/gr-usrp2/src/usrp2_base.h b/gr-usrp2/src/usrp2_base.h index df0c862f82..877437009f 100644 --- a/gr-usrp2/src/usrp2_base.h +++ b/gr-usrp2/src/usrp2_base.h @@ -63,6 +63,12 @@ public: */ bool sync_to_pps(); + + /*! + * \brief Read memory from Wishbone bus + */ + std::vector<uint8_t> peek(uint32_t addr, uint32_t len); + /*! * \brief Called by scheduler when starting flowgraph */ |