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authorJosh Blum <josh@joshknows.com>2010-10-28 17:22:25 -0700
committerJosh Blum <josh@joshknows.com>2010-10-28 17:22:25 -0700
commit2aef04843d248d0584b4865c62d7ca0772113dc9 (patch)
tree2d1e364da98634bec605f5882387e36bc034cfe0 /gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py
parent3dab5d93a45928baa4fb23878d644751e06943a0 (diff)
uhd: added ref clock option to single usrp blocks, minor grc fix on empty option keys
Diffstat (limited to 'gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py')
-rwxr-xr-xgr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py22
1 files changed, 22 insertions, 0 deletions
diff --git a/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py b/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py
index 9b6422f7a2..7337c71d7b 100755
--- a/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py
+++ b/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py
@@ -30,6 +30,13 @@ MAIN_TMPL = """\
io_type=uhd.io_type_t.\$type.type,
num_channels=\$nchan,
)
+\#if \$ref_clk()
+_clk_cfg = uhd.clock_config_t()
+_clk_cfg.ref_source = uhd.clock_config_t.REF_SMA
+_clk_cfg.pps_source = uhd.clock_config_t.PPS_SMA
+_clk_cfg.pps_polarity = uhd.clock_config_t.PPS_POS
+self.\$(id).set_clock_config(_clk_cfg);
+\#end if
\#if \$sd_spec()
self.\$(id).set_subdev_spec(\$sd_spec)
\#end if
@@ -104,6 +111,21 @@ self.\$(id).set_bandwidth(\$bw$(n), $n)
</hide>
</param>
<param>
+ <name>Ref Clock</name>
+ <key>ref_clk</key>
+ <value></value>
+ <type>enum</type>
+ <hide>\#if \$ref_clk() then 'none' else 'part'#</hide>
+ <option>
+ <name>External</name>
+ <key>ext</key>
+ </option>
+ <option>
+ <name>Internal</name>
+ <key></key>
+ </option>
+ </param>
+ <param>
<name>Subdev Spec</name>
<key>sd_spec</key>
<value></value>