Merged r6045:6116 from jcorgan/radar into trunk. Updates gr-radar-mono with work-in-progress.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6283 221aa14e-8319-0410-a670-987f0aec2ac5
author: jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> 2007-09-04 03:21:23 +0000
committer: jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> 2007-09-04 03:21:23 +0000
commit: 60d88c4aef7c5c1851028046eb67fdfe162c82c4 (patch)
tree: e8c742e863f34161acaa3b2f4fe95181233277f3 /gr-radar-mono/src/fpga/lib
parent: 1ef3a907f1d02d40ddc06f150d0524f01520f902 (diff)
6 files changed, 273 insertions, 39 deletions
diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am
index d9f5174a23..8aefd754d4 100644
--- a/gr-radar-mono/src/fpga/lib/Makefile.am
+++ b/gr-radar-mono/src/fpga/lib/Makefile.am
@@ -28,6 +28,7 @@ EXTRA_DIST = 			\
 		radar_tx.v	\
 		radar_rx.v	\
 		dac_interface.v	\
+		fifo32_4k.v	\
 		cordic_nco.v
 
 MOSTLYCLEANFILES = *~
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_4k.v b/gr-radar-mono/src/fpga/lib/fifo32_4k.v
new file mode 100644
index 0000000000..f31d020fdd
--- /dev/null
+++ b/gr-radar-mono/src/fpga/lib/fifo32_4k.v
@@ -0,0 +1,161 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: fifo32_4k.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo32_4k (
+	clock,
+	data,
+	rdreq,
+	sclr,
+	wrreq,
+	empty,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	  rdreq;
+	input	  sclr;
+	input	  wrreq;
+	output	  empty;
+	output	[31:0]  q;
+
+	wire  sub_wire0;
+	wire [31:0] sub_wire1;
+	wire  empty = sub_wire0;
+	wire [31:0] q = sub_wire1[31:0];
+
+	scfifo	scfifo_component (
+				.rdreq (rdreq),
+				.sclr (sclr),
+				.clock (clock),
+				.wrreq (wrreq),
+				.data (data),
+				.empty (sub_wire0),
+				.q (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.full (),
+				.usedw ()
+				// synopsys translate_on
+				);
+	defparam
+		scfifo_component.add_ram_output_register = "OFF",
+		scfifo_component.intended_device_family = "Cyclone",
+		scfifo_component.lpm_numwords = 4096,
+		scfifo_component.lpm_showahead = "OFF",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 32,
+		scfifo_component.lpm_widthu = 12,
+		scfifo_component.overflow_checking = "OFF",
+		scfifo_component.underflow_checking = "OFF",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_wave*.jpg TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v
index 2a0c08bb5c..127e9cee3a 100644
--- a/gr-radar-mono/src/fpga/lib/radar.v
+++ b/gr-radar-mono/src/fpga/lib/radar.v
@@ -22,8 +22,8 @@
 `include "../lib/radar_config.vh"
 
 module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
-	     tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
-	     rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
+	     tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
+	     rx_adc_i_i,rx_adc_q_i,
 	     rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
 
    // System interface
@@ -33,12 +33,12 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
    input 	 s_strobe_i;    // Configuration bus write
    
    // Transmit subsystem
+   output        tx_side_o;     // Transmitter slot
    output        tx_strobe_o;	// Generate an transmitter output sample
    output [13:0] tx_dac_i_o;	// I channel transmitter output to DAC
    output [13:0] tx_dac_q_o;    // Q channel transmitter output to DAC
-
+   
    // Receive subsystem
-   input         rx_strobe_i;	// Indicates receive sample ready from ADC
    input  [15:0] rx_adc_i_i;	// I channel input from ADC
    input  [15:0] rx_adc_q_i;	// Q channel input from ADC
    output 	 rx_strobe_o;	// Indicates output samples ready for Rx FIFO
@@ -47,6 +47,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    // Application control
    wire          reset;		// Master application reset
+   wire          tx_side;	// Transmitter slot
+   wire          debug_enabled; // Enable debugging mode; 	 
    wire 	 tx_enable;     // Transmitter enable
    wire 	 rx_enable;     // Receiver enable
    wire          tx_ctrl;       // Transmitter on control
@@ -59,7 +61,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    radar_control controller
      (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
-      .reset_o(reset),.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
+      .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
+      .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
       .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr));
 
    radar_tx transmitter
@@ -68,8 +71,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
        .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
    
    radar_rx receiver
-     ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl & 1'b0), // Disable receiver for now
-       .strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
+     ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled),
+       .rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
        .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
    
 endmodule // radar
diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh
index a06a511195..251b2dba30 100644
--- a/gr-radar-mono/src/fpga/lib/radar_config.vh
+++ b/gr-radar-mono/src/fpga/lib/radar_config.vh
@@ -23,7 +23,13 @@
 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
 
 `define FR_RADAR_MODE           `FR_USER_0
-`define bmFR_RADAR_MODE_RESET	32'h0001
+`define bmFR_RADAR_MODE_RESET	32'b1 << 0
+`define bmFR_RADAR_TXSIDE       32'b1 << 1
+`define bmFR_RADAR_LOOP         32'b1 << 2
+`define bmFR_RADAR_META         32'b1 << 3
+`define bmFR_RADAR_DERAMP       32'b1 << 4
+`define bmFR_RADAR_CHIRPS       32'b11 << 5
+`define bmFR_RADAR_DEBUG        32'b1 << 7
 
 `define FR_RADAR_TON            `FR_USER_1
 `define FR_RADAR_TSW            `FR_USER_2
@@ -32,4 +38,3 @@
 `define FR_RADAR_AMPL           `FR_USER_5
 `define FR_RADAR_FSTART         `FR_USER_6
 `define FR_RADAR_FINCR          `FR_USER_7
-
diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
index 4f88645bb2..e22da962d6 100644
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ b/gr-radar-mono/src/fpga/lib/radar_control.v
@@ -22,7 +22,8 @@
 `include "../lib/radar_config.vh"
 
 module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
-		     reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
+		     reset_o,tx_side_o,dbg_o,
+		     tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
 		     ampl_o,fstart_o,fincr_o);
 
    // System interface
@@ -33,6 +34,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    // Control and configuration outputs
    output 	 reset_o;
+   output        tx_side_o;
+   output        dbg_o;
    output        tx_strobe_o;
    output        tx_ctrl_o;
    output        rx_ctrl_o;
@@ -42,8 +45,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    
    // Internal configuration
    wire 	 lp_ena;
-   wire 	 dr_ena;
    wire 	 md_ena;
+   wire 	 dr_ena;
    wire   [1:0]  chirps;
    wire   [15:0] t_on;
    wire   [15:0] t_sw;
@@ -51,9 +54,17 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    wire   [31:0] t_idle;
 
    // Configuration from host
+   wire [31:0] 	 mode;
    setting_reg #(`FR_RADAR_MODE)   sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-					   .out({chirps,md_ena,dr_ena,lp_ena,reset_o}));
-   				     
+					   .out(mode));
+   assign reset_o   = mode[0];
+   assign tx_side_o = mode[1];
+   assign lp_ena    = mode[2];
+   assign md_ena    = mode[3];
+   assign dr_ena    = mode[4];
+   assign chirps    = mode[6:5];
+   assign dbg_o     = mode[7];
+   
    setting_reg #(`FR_RADAR_TON)    sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
 					  .out(t_on));
    
@@ -108,7 +119,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 		count <= 32'b0;
 	     end
 	   else
-	     count <= count + 24'b1;
+	     count <= count + 32'b1;
 
 	 `ST_LOOK:
 	   if (count == {16'b0,t_look})
@@ -123,7 +134,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 	   if (count == t_idle)
 	     begin
 		state <= `ST_ON;
-		count <= 24'b0;
+		count <= 32'b0;
 	     end
 	   else
 	     count <= count + 32'b1;
diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v
index b559df6995..1ca5461340 100644
--- a/gr-radar-mono/src/fpga/lib/radar_rx.v
+++ b/gr-radar-mono/src/fpga/lib/radar_rx.v
@@ -22,43 +22,96 @@
 `include "../../../../usrp/firmware/include/fpga_regs_common.v"
 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
 
-module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,
-		rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
+module radar_rx(clk_i,rst_i,ena_i,dbg_i,
+		rx_in_i_i,rx_in_q_i,
+		rx_i_o,rx_q_o,rx_strobe_o);
    
    input clk_i;
    input rst_i;
    input ena_i;
-   input strobe_i;
-
-   input [6:0] saddr_i;
-   input [31:0] sdata_i;
-   input s_strobe_i;
-
+   input dbg_i;
+   
    input [15:0] rx_in_i_i;
    input [15:0] rx_in_q_i;
    
    output [15:0] rx_i_o;
    output [15:0] rx_q_o;
-   output rx_strobe_o;
+   output reg    rx_strobe_o;
 
-   // Just count up for debugging
-   reg [31:0] counter;
+   reg [15:0] count;
 
    always @(posedge clk_i)
-     begin
-	if (rst_i | ~ena_i)
-	  counter <= 32'b0;
-	else if (strobe_i & rx_strobe_o)
-	  counter <= counter + 32'b1;
-     end
+     if (rst_i | ~ena_i)
+       count <= 16'b0;
+     else
+       count <= count + 16'b1;
+
+   wire [31:0] fifo_data = dbg_i ? {count[15:0],16'hAA55} : {rx_in_i_i,rx_in_q_i};
+
+   // Need to buffer received samples as they come in at 32 bits per cycle
+   // but the rx_buffer.v fifo is only 16 bits wide.
+   //
+   reg         fifo_read;
+   wire [31:0] fifo_out;
+   wire        fifo_empty;
+   
+   fifo32_4k fifo(.clock(clk_i),.sclr(rst_i),
+		  .data(fifo_data),.wrreq(ena_i),
+		  .q(fifo_out),.rdreq(fifo_read),
+		  .empty(fifo_empty) );
+
+   `define ST_RD_IDLE     4'b0001
+   `define ST_RD_REQ      4'b0010
+   `define ST_WR_FIFO     4'b0100
+   `define ST_RD_DELAY    4'b1000
+
+   reg [3:0] state;
+   reg [3:0] delay;
+   
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+	  state <= `ST_RD_IDLE;
+	  delay <= 4'd0;
+	  rx_strobe_o <= 1'b0;
+	  fifo_read <= 1'b0;
+       end
+     else
+       case (state)
+	 `ST_RD_IDLE:
+	   begin
+	      if (!fifo_empty)
+		begin
+		   fifo_read <= 1'b1;
+		   state <= `ST_RD_REQ;
+		end
+	   end
+
+	 `ST_RD_REQ:
+	   begin
+	      fifo_read <= 1'b0;
+	      rx_strobe_o <= 1'b1;
+	      state <= `ST_WR_FIFO;
+	   end
+
+	 `ST_WR_FIFO:
+	   begin
+	      rx_strobe_o <= 1'b0;
+	      state <= `ST_RD_DELAY;
+	   end
+
+	 `ST_RD_DELAY:
+	   if (delay == 7)
+	     begin
+		delay <= 0;
+		state <= `ST_RD_IDLE;
+	     end
+	   else
+	     delay <= delay + 1'b1;
 
-   assign rx_i_o = ena_i ? counter[31:16] : 16'b0;
-   assign rx_q_o = ena_i ? counter[15:0] : 16'b0;
+       endcase // case(state)
    
-   // Temporarily we duplicate what master_control.v did to generate decim_strobe
-   // so we can do receive debugging. Later we'll drive rx_strobe_o in bursts to
-   // load receiver data into the rx fifo.
-   strobe_gen rx_strobe_gen
-     ( .clock(clk_i),.reset(rst_i),.enable(ena_i),.rate(7),.strobe_in(strobe_i),.strobe(rx_strobe_o) );
+   assign rx_i_o = fifo_out[31:16];
+   assign rx_q_o = fifo_out[15:0];
    
 endmodule // radar_rx
author	jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>	2007-09-04 03:21:23 +0000
committer	jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>	2007-09-04 03:21:23 +0000
commit	60d88c4aef7c5c1851028046eb67fdfe162c82c4 (patch)
tree	e8c742e863f34161acaa3b2f4fe95181233277f3 /gr-radar-mono/src/fpga/lib
parent	1ef3a907f1d02d40ddc06f150d0524f01520f902 (diff)