diff options
| author | Tom Rondeau <tom@trondeau.com> | 2014-12-29 13:07:03 -0500 |
|---|---|---|
| committer | Tom Rondeau <tom@trondeau.com> | 2014-12-29 13:07:03 -0500 |
| commit | ccebbe0a028158df250aae02c1dd893dd1551dda (patch) | |
| tree | 7fef8be51ce8daea9a27504f8bc9d9396cac4208 /gr-blocks/python | |
| parent | d0d286d33d2dd2b1c3f0813a9703f600f692943f (diff) | |
blocks: added endianness toggle to repack bits.
Diffstat (limited to 'gr-blocks/python')
| -rwxr-xr-x | gr-blocks/python/blocks/qa_repack_bits_bb.py | 53 |
1 files changed, 52 insertions, 1 deletions
diff --git a/gr-blocks/python/blocks/qa_repack_bits_bb.py b/gr-blocks/python/blocks/qa_repack_bits_bb.py index 10880b196a..50e1506196 100755 --- a/gr-blocks/python/blocks/qa_repack_bits_bb.py +++ b/gr-blocks/python/blocks/qa_repack_bits_bb.py @@ -46,6 +46,19 @@ class qa_repack_bits_bb (gr_unittest.TestCase): self.tb.run () self.assertEqual(sink.data(), expected_data) + def test_001_simple_msb (self): + """ Very simple test, 2 bits -> 1 with MSB set """ + src_data = (0b11, 0b01, 0b10) + expected_data = (0b1, 0b1, 0b0, 0b1, 0b1, 0b0) + k = 2 + l = 1 + src = blocks.vector_source_b(src_data, False, 1) + repack = blocks.repack_bits_bb(k, l, "", False, gr.GR_MSB_FIRST) + sink = blocks.vector_sink_b() + self.tb.connect(src, repack, sink) + self.tb.run () + self.assertEqual(sink.data(), expected_data) + def test_002_three (self): """ 8 -> 3 """ src_data = (0b11111101, 0b11111111, 0b11111111) @@ -59,6 +72,32 @@ class qa_repack_bits_bb (gr_unittest.TestCase): self.tb.run () self.assertEqual(sink.data(), expected_data) + def test_002_three (self): + """ 8 -> 3 """ + src_data = (0b11111101, 0b11111111, 0b11111111) + expected_data = (0b101,) + (0b111,) * 7 + k = 8 + l = 3 + src = blocks.vector_source_b(src_data, False, 1) + repack = blocks.repack_bits_bb(k, l) + sink = blocks.vector_sink_b() + self.tb.connect(src, repack, sink) + self.tb.run () + self.assertEqual(sink.data(), expected_data) + + def test_002_three_msb (self): + """ 8 -> 3 """ + src_data = (0b11111101, 0b11111111, 0b11111111) + expected_data = (0b111,) + (0b111,) + (0b011,) + (0b111,) * 5 + k = 8 + l = 3 + src = blocks.vector_source_b(src_data, False, 1) + repack = blocks.repack_bits_bb(k, l, "", False, gr.GR_MSB_FIRST) + sink = blocks.vector_sink_b() + self.tb.connect(src, repack, sink) + self.tb.run () + self.assertEqual(sink.data(), expected_data) + def test_003_lots_of_bytes (self): """ Lots and lots of bytes, multiple packer stages """ src_data = tuple([random.randint(0, 255) for x in range(3*5*7*8 * 10)]) @@ -72,6 +111,19 @@ class qa_repack_bits_bb (gr_unittest.TestCase): self.tb.run () self.assertEqual(sink.data(), src_data) + def test_003_lots_of_bytes_msb (self): + """ Lots and lots of bytes, multiple packer stages """ + src_data = tuple([random.randint(0, 255) for x in range(3*5*7*8 * 10)]) + src = blocks.vector_source_b(src_data, False, 1) + repack1 = blocks.repack_bits_bb(8, 3, "", False, gr.GR_MSB_FIRST) + repack2 = blocks.repack_bits_bb(3, 5, "", False, gr.GR_MSB_FIRST) + repack3 = blocks.repack_bits_bb(5, 7, "", False, gr.GR_MSB_FIRST) + repack4 = blocks.repack_bits_bb(7, 8, "", False, gr.GR_MSB_FIRST) + sink = blocks.vector_sink_b() + self.tb.connect(src, repack1, repack2, repack3, repack4, sink) + self.tb.run () + self.assertEqual(sink.data(), src_data) + def test_004_three_with_tags (self): """ 8 -> 3 """ src_data = (0b11111101, 0b11111111) @@ -112,4 +164,3 @@ class qa_repack_bits_bb (gr_unittest.TestCase): if __name__ == '__main__': gr_unittest.run(qa_repack_bits_bb, "qa_repack_bits_bb.xml") - |