diff options
| author | Tom Rondeau <tom@trondeau.com> | 2014-07-07 12:18:00 -0400 |
|---|---|---|
| committer | Tom Rondeau <tom@trondeau.com> | 2014-07-07 12:18:00 -0400 |
| commit | 597b93798a804cde1783d6d2ab53b348d57c44cd (patch) | |
| tree | b65e73bb0de634ff5d209b15971ebdabf369a45c /gr-atsc | |
| parent | 1151e5502ccd440ebd89599cf7e4be4fb5ed8334 (diff) | |
Removing trailing/extra whitespaces before release.
We should be more careful about letting these into the code in the future. In emacs, we can use (add-hook 'before-save-hook 'delete-trailing-whitespace).
Diffstat (limited to 'gr-atsc')
| -rw-r--r-- | gr-atsc/lib/atsc_bit_timing_loop.cc | 2 | ||||
| -rwxr-xr-x | gr-atsc/python/atsc/atsc_rx.py | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/gr-atsc/lib/atsc_bit_timing_loop.cc b/gr-atsc/lib/atsc_bit_timing_loop.cc index f75e724834..1458c9ed63 100644 --- a/gr-atsc/lib/atsc_bit_timing_loop.cc +++ b/gr-atsc/lib/atsc_bit_timing_loop.cc @@ -120,6 +120,6 @@ atsc_bit_timing_loop::work (int noutput_items, out_tag[k] = tag; } - + return k; } diff --git a/gr-atsc/python/atsc/atsc_rx.py b/gr-atsc/python/atsc/atsc_rx.py index 377c4daa29..940eeac4bd 100755 --- a/gr-atsc/python/atsc/atsc_rx.py +++ b/gr-atsc/python/atsc/atsc_rx.py @@ -28,7 +28,7 @@ # -s output shorts # # This python script converts from interleaved shorts to the complex data type, -# then multiplies the sample rate by 3, from 6.4e6 to 19.2e6 +# then multiplies the sample rate by 3, from 6.4e6 to 19.2e6 # complex samples / sec, then lowpass filters with a cutoff of 3.2MHz # and a transition band width of .5MHz. Center of the tv channels is # now at 0 with edges at -3.2MHz and 3.2MHz. This puts the pilot at @@ -38,7 +38,7 @@ # not stored in the phase with atsc ), this is then feed to the bit lock # loop, this looks for the bit sync marker put at the beginning of every segment # field, this then adjusts the timing so the amplitude will be sampled at the -# correct sample ( sub-sample is used in this case ). +# correct sample ( sub-sample is used in this case ). # # Output is float. @@ -82,7 +82,7 @@ def graph (args): # Move the center frequency to 5.75MHz ( this wont be needed soon ) duc_coeffs = filter.firdes.low_pass ( 1, 19.2e6, 9e6, 1e6, filter.firdes.WIN_HAMMING ) duc = filter.freq_xlating_fir_filter_ccf ( 1, duc_coeffs, -5.75e6, 19.2e6 ) - + # fpll input is float c2f = blocks.complex_to_float() |