GNU Radio 3.3.0 C++ API
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00001 /* 00002 * USRP - Universal Software Radio Peripheral 00003 * 00004 * Copyright (C) 2003 Free Software Foundation, Inc. 00005 * 00006 * This program is free software; you can redistribute it and/or modify 00007 * it under the terms of the GNU General Public License as published by 00008 * the Free Software Foundation; either version 3 of the License, or 00009 * (at your option) any later version. 00010 * 00011 * This program is distributed in the hope that it will be useful, 00012 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 * GNU General Public License for more details. 00015 * 00016 * You should have received a copy of the GNU General Public License 00017 * along with this program; if not, write to the Free Software 00018 * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 00019 */ 00020 00021 /* 00022 * These are the register definitions for the Rev 1 USRP prototype 00023 * The Rev 1 is the version with the AD9862's and daughterboards 00024 */ 00025 00026 #ifndef _USRP_REV1_REGS_H_ 00027 #define _USRP_REV1_REGS_H_ 00028 00029 #include "fx2regs.h" 00030 00031 /* 00032 * Port A (bit addressable): 00033 */ 00034 00035 #define USRP_PA IOA // Port A 00036 #define USRP_PA_OE OEA // Port A direction register 00037 00038 #define bmPA_S_CLK bmBIT0 // SPI serial clock 00039 #define bmPA_S_DATA_TO_PERIPH bmBIT1 // SPI SDI (peripheral rel name) 00040 #define bmPA_S_DATA_FROM_PERIPH bmBIT2 // SPI SDO (peripheral rel name) 00041 #define bmPA_SEN_FPGA bmBIT3 // serial enable for FPGA (active low) 00042 #define bmPA_SEN_CODEC_A bmBIT4 // serial enable AD9862 A (active low) 00043 #define bmPA_SEN_CODEC_B bmBIT5 // serial enable AD9862 B (active low) 00044 //#define bmPA_FX2_2 bmBIT6 // misc pin to FPGA (overflow) 00045 //#define bmPA_FX2_3 bmBIT7 // misc pin to FPGA (underflow) 00046 #define bmPA_RX_OVERRUN bmBIT6 // misc pin to FPGA (overflow) 00047 #define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow) 00048 00049 00050 sbit at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A 00051 sbit at 0x80+1 bitS_OUT; // out from FX2 point of view 00052 sbit at 0x80+2 bitS_IN; // in from FX2 point of view 00053 00054 00055 /* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */ 00056 00057 #define bmPORT_A_OUTPUTS (bmPA_S_CLK \ 00058 | bmPA_S_DATA_TO_PERIPH \ 00059 | bmPA_SEN_FPGA \ 00060 | bmPA_SEN_CODEC_A \ 00061 | bmPA_SEN_CODEC_B \ 00062 ) 00063 00064 #define bmPORT_A_INITIAL (bmPA_SEN_FPGA | bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B) 00065 00066 00067 /* Port B: GPIF FD[7:0] */ 00068 00069 /* 00070 * Port C (bit addressable): 00071 * 5:1 FPGA configuration 00072 */ 00073 00074 #define USRP_PC IOC // Port C 00075 #define USRP_PC_OE OEC // Port C direction register 00076 00077 #define USRP_ALTERA_CONFIG USRP_PC 00078 00079 #define bmPC_nRESET bmBIT0 // reset line to codecs (active low) 00080 #define bmALTERA_DATA0 bmBIT1 00081 #define bmALTERA_NCONFIG bmBIT2 00082 #define bmALTERA_DCLK bmBIT3 00083 #define bmALTERA_CONF_DONE bmBIT4 00084 #define bmALTERA_NSTATUS bmBIT5 00085 #define bmPC_LED0 bmBIT6 // active low 00086 #define bmPC_LED1 bmBIT7 // active low 00087 00088 sbit at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C 00089 sbit at 0xA0+3 bitALTERA_DCLK; 00090 00091 00092 #define bmALTERA_BITS (bmALTERA_DATA0 \ 00093 | bmALTERA_NCONFIG \ 00094 | bmALTERA_DCLK \ 00095 | bmALTERA_CONF_DONE \ 00096 | bmALTERA_NSTATUS) 00097 00098 #define bmPORT_C_OUTPUTS (bmPC_nRESET \ 00099 | bmALTERA_DATA0 \ 00100 | bmALTERA_NCONFIG \ 00101 | bmALTERA_DCLK \ 00102 | bmPC_LED0 \ 00103 | bmPC_LED1 \ 00104 ) 00105 00106 #define bmPORT_C_INITIAL (bmPC_LED0 | bmPC_LED1) 00107 00108 00109 #define USRP_LED_REG USRP_PC 00110 #define bmLED0 bmPC_LED0 00111 #define bmLED1 bmPC_LED1 00112 00113 00114 /* Port D: GPIF FD[15:8] */ 00115 00116 /* Port E: not bit addressible */ 00117 00118 #define USRP_PE IOE // Port E 00119 #define USRP_PE_OE OEE // Port E direction register 00120 00121 #define bmPE_PE0 bmBIT0 // GPIF debug output 00122 #define bmPE_PE1 bmBIT1 // GPIF debug output 00123 #define bmPE_PE2 bmBIT2 // GPIF debug output 00124 #define bmPE_FPGA_CLR_STATUS bmBIT3 // misc pin to FPGA (clear status) 00125 #define bmPE_SEN_TX_A bmBIT4 // serial enable d'board TX A (active low) 00126 #define bmPE_SEN_RX_A bmBIT5 // serial enable d'board RX A (active low) 00127 #define bmPE_SEN_TX_B bmBIT6 // serial enable d'board TX B (active low) 00128 #define bmPE_SEN_RX_B bmBIT7 // serial enable d'board RX B (active low) 00129 00130 00131 #define bmPORT_E_OUTPUTS (bmPE_FPGA_CLR_STATUS \ 00132 | bmPE_SEN_TX_A \ 00133 | bmPE_SEN_RX_A \ 00134 | bmPE_SEN_TX_B \ 00135 | bmPE_SEN_RX_B \ 00136 ) 00137 00138 00139 #define bmPORT_E_INITIAL (bmPE_SEN_TX_A \ 00140 | bmPE_SEN_RX_A \ 00141 | bmPE_SEN_TX_B \ 00142 | bmPE_SEN_RX_B \ 00143 ) 00144 00145 /* 00146 * FPGA output lines that are tied to FX2 RDYx inputs. 00147 * These are readable using GPIFREADYSTAT. 00148 */ 00149 #define bmFPGA_HAS_SPACE bmBIT0 // usbrdy[0] has room for 512 byte packet 00150 #define bmFPGA_PKT_AVAIL bmBIT1 // usbrdy[1] has >= 512 bytes available 00151 // #define bmTX_UNDERRUN bmBIT2 // usbrdy[2] D/A ran out of data 00152 // #define bmRX_OVERRUN bmBIT3 // usbrdy[3] A/D ran out of buffer 00153 00154 /* 00155 * FPGA input lines that are tied to the FX2 CTLx outputs. 00156 * 00157 * These are controlled by the GPIF microprogram... 00158 */ 00159 // WR bmBIT0 // usbctl[0] 00160 // RD bmBIT1 // usbctl[1] 00161 // OE bmBIT2 // usbctl[2] 00162 00163 #endif /* _USRP_REV1_REGS_H_ */