From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan <jcorgan@corganenterprises.com>
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
---
usrp/fpga/sdr_lib/sign_extend.v | 35 -----------------------------------
1 file changed, 35 deletions(-)
delete mode 100644 usrp/fpga/sdr_lib/sign_extend.v
(limited to 'usrp/fpga/sdr_lib/sign_extend.v')
diff --git a/usrp/fpga/sdr_lib/sign_extend.v b/usrp/fpga/sdr_lib/sign_extend.v
deleted file mode 100644
index eae67faf28..0000000000
--- a/usrp/fpga/sdr_lib/sign_extend.v
+++ /dev/null
@@ -1,35 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2003 Matt Ettus
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-
-// Sign extension "macro"
-// bits_out should be greater than bits_in
-
-module sign_extend (in,out);
- parameter bits_in=0; // FIXME Quartus insists on a default
- parameter bits_out=0;
-
- input [bits_in-1:0] in;
- output [bits_out-1:0] out;
-
- assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
-
-endmodule
--
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