From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan <jcorgan@corganenterprises.com>
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
---
usrp/fpga/sdr_lib/rx_dcoffset.v | 22 ----------------------
1 file changed, 22 deletions(-)
delete mode 100644 usrp/fpga/sdr_lib/rx_dcoffset.v
(limited to 'usrp/fpga/sdr_lib/rx_dcoffset.v')
diff --git a/usrp/fpga/sdr_lib/rx_dcoffset.v b/usrp/fpga/sdr_lib/rx_dcoffset.v
deleted file mode 100644
index 3be475ed60..0000000000
--- a/usrp/fpga/sdr_lib/rx_dcoffset.v
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-module rx_dcoffset (input clock, input enable, input reset,
- input signed [15:0] adc_in, output signed [15:0] adc_out,
- input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
- parameter MYADDR = 0;
-
- reg signed [31:0] integrator;
- wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
- assign adc_out = adc_in - scaled_integrator;
-
- // FIXME do we need signed?
- //FIXME What do we do when clipping?
- always @(posedge clock)
- if(reset)
- integrator <= #1 32'd0;
- else if(serial_strobe & (MYADDR == serial_addr))
- integrator <= #1 {serial_data[15:0],16'd0};
- else if(enable)
- integrator <= #1 integrator + adc_out;
-
-endmodule // rx_dcoffset
--
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