From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan <jcorgan@corganenterprises.com> Date: Sun, 28 Feb 2010 12:47:43 -0800 Subject: Remove usrp1 and usrp2 FPGA files. These are now hosted at: git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories. --- usrp/fpga/sdr_lib/ram.v | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 usrp/fpga/sdr_lib/ram.v (limited to 'usrp/fpga/sdr_lib/ram.v') diff --git a/usrp/fpga/sdr_lib/ram.v b/usrp/fpga/sdr_lib/ram.v deleted file mode 100644 index fb64cdeae1..0000000000 --- a/usrp/fpga/sdr_lib/ram.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module ram (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr, output reg [15:0] rd_data); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data <= #1 ram_array[rd_addr]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram -- cgit v1.2.3