From e18740dee59e76432fd1ff62feadf7ad77215c1d Mon Sep 17 00:00:00 2001
From: Johnathan Corgan <jcorgan@corganenterprises.com>
Date: Sun, 3 Jul 2011 16:01:08 -0700
Subject: radar-mono: removed from tree, obsolete

---
 gr-radar-mono/src/fpga/top/.gitignore          |  21 --
 gr-radar-mono/src/fpga/top/Makefile.am         |  48 ---
 gr-radar-mono/src/fpga/top/config.vh           |  24 --
 gr-radar-mono/src/fpga/top/dacpll.v            | 291 ----------------
 gr-radar-mono/src/fpga/top/usrp_radar_mono.csf | 444 -------------------------
 gr-radar-mono/src/fpga/top/usrp_radar_mono.esf |  14 -
 gr-radar-mono/src/fpga/top/usrp_radar_mono.psf | 312 -----------------
 gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf |  29 --
 gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf | 402 ----------------------
 gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf | Bin 122609 -> 0 bytes
 gr-radar-mono/src/fpga/top/usrp_radar_mono.srf |  65 ----
 gr-radar-mono/src/fpga/top/usrp_radar_mono.v   | 213 ------------
 12 files changed, 1863 deletions(-)
 delete mode 100644 gr-radar-mono/src/fpga/top/.gitignore
 delete mode 100644 gr-radar-mono/src/fpga/top/Makefile.am
 delete mode 100644 gr-radar-mono/src/fpga/top/config.vh
 delete mode 100644 gr-radar-mono/src/fpga/top/dacpll.v
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.csf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.esf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.psf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
 delete mode 100644 gr-radar-mono/src/fpga/top/usrp_radar_mono.v

(limited to 'gr-radar-mono/src/fpga/top')

diff --git a/gr-radar-mono/src/fpga/top/.gitignore b/gr-radar-mono/src/fpga/top/.gitignore
deleted file mode 100644
index 40492321d8..0000000000
--- a/gr-radar-mono/src/fpga/top/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-/*.qmsg
-/*.qws
-/*.eqn
-/*.done
-/*.htm
-/*.rpt
-/*.ini
-/*.fsf
-/*.jam
-/*.jbc
-/*.pin
-/*.pof
-/*.rbf
-/*.smsg
-/*.sof
-/*.ttf
-/*.summary
-/undo_redo.txt
-/db
-/Makefile
-/Makefile.in
diff --git a/gr-radar-mono/src/fpga/top/Makefile.am b/gr-radar-mono/src/fpga/top/Makefile.am
deleted file mode 100644
index 51f73ebfe5..0000000000
--- a/gr-radar-mono/src/fpga/top/Makefile.am
+++ /dev/null
@@ -1,48 +0,0 @@
-#
-# Copyright 2007,2009 Free Software Foundation, Inc.
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
-
-include $(top_srcdir)/Makefile.common
-
-RBFS = usrp_radar_mono.rbf
-
-rbf2datadir = $(prefix)/share/usrp/rev2
-dist_rbf2data_DATA = $(RBFS)
-
-rbf4datadir = $(prefix)/share/usrp/rev4
-dist_rbf4data_DATA = $(RBFS)
-
-EXTRA_DIST += \
-	usrp_radar_mono.csf \
-	usrp_radar_mono.esf \
-	usrp_radar_mono.psf \
-	usrp_radar_mono.qpf \
-	usrp_radar_mono.qsf \
-	usrp_radar_mono.v
-
-MOSTLYCLEANFILES += 	\
-	db/*		\
-	*.rpt		\
-	*.summary	\
-	*.qws		\
-	*.smsg		\
-	*.done		\
-	*.pin		\
-	*.sof
diff --git a/gr-radar-mono/src/fpga/top/config.vh b/gr-radar-mono/src/fpga/top/config.vh
deleted file mode 100644
index 1769794123..0000000000
--- a/gr-radar-mono/src/fpga/top/config.vh
+++ /dev/null
@@ -1,24 +0,0 @@
-// -*- verilog -*-
-//
-//  USRP - Universal Software Radio Peripheral
-//
-//  Copyright (C) 2007 Corgan Enterprises LLC
-//
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
-//
-
-// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz
-//`define TX_RATE_MAX
-
diff --git a/gr-radar-mono/src/fpga/top/dacpll.v b/gr-radar-mono/src/fpga/top/dacpll.v
deleted file mode 100644
index f3941bc67a..0000000000
--- a/gr-radar-mono/src/fpga/top/dacpll.v
+++ /dev/null
@@ -1,291 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: dacpll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.0 Build 33 02/05/2007 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module dacpll (
-	areset,
-	inclk0,
-	c0);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c0;
-
-	wire [5:0] sub_wire0;
-	wire [0:0] sub_wire4 = 1'h0;
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  sub_wire2 = inclk0;
-	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
-	altpll	altpll_component (
-				.inclk (sub_wire3),
-				.areset (areset),
-				.clk (sub_wire0),
-				.activeclock (),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b1),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbout (),
-				.locked (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
-		altpll_component.clk0_phase_shift = "0000",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.inclk0_input_frequency = 15625,
-		altpll_component.intended_device_family = "Cyclone",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_USED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_UNUSED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_UNUSED",
-		altpll_component.port_clk3 = "PORT_UNUSED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf
deleted file mode 100644
index 121b15aaf0..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf
+++ /dev/null
@@ -1,444 +0,0 @@
-COMPILER_SETTINGS
-{
-	IO_PLACEMENT_OPTIMIZATION = OFF;
-	ENABLE_DRC_SETTINGS = OFF;
-	PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
-	PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
-	PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
-	DRC_FANOUT_EXCEEDING = 30;
-	DRC_REPORT_FANOUT_EXCEEDING = OFF;
-	DRC_TOP_FANOUT = 50;
-	DRC_REPORT_TOP_FANOUT = OFF;
-	RUN_DRC_DURING_COMPILATION = OFF;
-	ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
-	ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
-	ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
-	ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
-	SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
-	MERGE_HEX_FILE = OFF;
-	TRUE_WYSIWYG_FLOW = OFF;
-	SEED = 1;
-	FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
-	FAMILY = Cyclone;
-	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
-	DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
-	DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
-	DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
-	DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
-	DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
-	DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
-	STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
-	PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
-	PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
-	STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
-	FAST_FIT_COMPILATION = OFF;
-	SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
-	OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
-	OPTIMIZE_TIMING = "NORMAL COMPILATION";
-	OPTIMIZE_HOLD_TIMING = OFF;
-	COMPILATION_LEVEL = FULL;
-	SAVE_DISK_SPACE = OFF;
-	SPEED_DISK_USAGE_TRADEOFF = NORMAL;
-	LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
-	SIGNALPROBE_ALLOW_OVERUSE = OFF;
-	FOCUS_ENTITY_NAME = |usrp_radar_mono;
-	ROUTING_BACK_ANNOTATION_MODE = OFF;
-	INC_PLC_MODE = OFF;
-	FIT_ONLY_ONE_ATTEMPT = OFF;
-}
-DEFAULT_DEVICE_OPTIONS
-{
-	GENERATE_CONFIG_HEXOUT_FILE = OFF;
-	GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
-	GENERATE_CONFIG_JBC_FILE = OFF;
-	GENERATE_CONFIG_JAM_FILE = OFF;
-	GENERATE_CONFIG_ISC_FILE = OFF;
-	GENERATE_CONFIG_SVF_FILE = OFF;
-	GENERATE_JBC_FILE_COMPRESSED = ON;
-	GENERATE_JBC_FILE = OFF;
-	GENERATE_JAM_FILE = OFF;
-	GENERATE_ISC_FILE = OFF;
-	GENERATE_SVF_FILE = OFF;
-	RESERVE_PIN = "AS INPUT TRI-STATED";
-	RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
-	HEXOUT_FILE_COUNT_DIRECTION = UP;
-	HEXOUT_FILE_START_ADDRESS = 0;
-	GENERATE_HEX_FILE = OFF;
-	GENERATE_RBF_FILE = OFF;
-	GENERATE_TTF_FILE = OFF;
-	RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
-	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
-	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
-	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
-	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_CONFIGURATION_DEVICE = AUTO;
-	CYCLONE_CONFIGURATION_DEVICE = AUTO;
-	FLEX10K_CONFIGURATION_DEVICE = AUTO;
-	FLEX6K_CONFIGURATION_DEVICE = AUTO;
-	MERCURY_CONFIGURATION_DEVICE = AUTO;
-	EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
-	APEX20K_CONFIGURATION_DEVICE = AUTO;
-	USE_CONFIGURATION_DEVICE = ON;
-	ENABLE_INIT_DONE_OUTPUT = OFF;
-	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
-	ENABLE_DEVICE_WIDE_OE = OFF;
-	ENABLE_DEVICE_WIDE_RESET = OFF;
-	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
-	AUTO_RESTART_CONFIGURATION = OFF;
-	ENABLE_VREFB_PIN = OFF;
-	ENABLE_VREFA_PIN = OFF;
-	SECURITY_BIT = OFF;
-	USER_START_UP_CLOCK = OFF;
-	APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
-	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	STRATIX_UPDATE_MODE = STANDARD;
-	USE_CHECKSUM_AS_USERCODE = OFF;
-	MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
-	MAX7000_JTAG_USER_CODE = FFFFFFFF;
-	FLEX10K_JTAG_USER_CODE = 7F;
-	MERCURY_JTAG_USER_CODE = FFFFFFFF;
-	APEX20K_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_JTAG_USER_CODE = FFFFFFFF;
-	MAX7000S_JTAG_USER_CODE = FFFF;
-	RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
-	ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
-	ENABLE_JTAG_BST_SUPPORT = OFF;
-	CONFIGURATION_CLOCK_DIVISOR = 1;
-	CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
-	CLOCK_SOURCE = INTERNAL;
-	COMPRESSION_MODE = OFF;
-	ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
-}
-AUTO_SLD_HUB_ENTITY
-{
-	AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
-	HUB_INSTANCE_NAME = SLD_HUB_INST;
-	HUB_ENTITY_NAME = SLD_HUB;
-}
-SIGNALTAP_LOGIC_ANALYZER_SETTINGS
-{
-	ENABLE_SIGNALTAP = Off;
-	AUTO_ENABLE_SMART_COMPILE = On;
-}
-CHIP(usrp_radar_mono)
-{
-	DEVICE = EP1C12Q240C8;
-	DEVICE_FILTER_PACKAGE = "ANY QFP";
-	DEVICE_FILTER_PIN_COUNT = 240;
-	DEVICE_FILTER_SPEED_GRADE = ANY;
-	AUTO_RESTART_CONFIGURATION = OFF;
-	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
-	USER_START_UP_CLOCK = OFF;
-	ENABLE_DEVICE_WIDE_RESET = OFF;
-	ENABLE_DEVICE_WIDE_OE = OFF;
-	ENABLE_INIT_DONE_OUTPUT = OFF;
-	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
-	ENABLE_JTAG_BST_SUPPORT = OFF;
-	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
-	APEX20K_JTAG_USER_CODE = FFFFFFFF;
-	MERCURY_JTAG_USER_CODE = FFFFFFFF;
-	FLEX10K_JTAG_USER_CODE = 7F;
-	MAX7000_JTAG_USER_CODE = FFFFFFFF;
-	MAX7000S_JTAG_USER_CODE = FFFF;
-	STRATIX_JTAG_USER_CODE = FFFFFFFF;
-	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	USE_CONFIGURATION_DEVICE = OFF;
-	APEX20K_CONFIGURATION_DEVICE = AUTO;
-	MERCURY_CONFIGURATION_DEVICE = AUTO;
-	FLEX6K_CONFIGURATION_DEVICE = AUTO;
-	FLEX10K_CONFIGURATION_DEVICE = AUTO;
-	EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
-	STRATIX_CONFIGURATION_DEVICE = AUTO;
-	CYCLONE_CONFIGURATION_DEVICE = AUTO;
-	STRATIX_UPDATE_MODE = STANDARD;
-	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
-	DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
-	COMPRESSION_MODE = OFF;
-	ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
-	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
-	USE_CHECKSUM_AS_USERCODE = OFF;
-	MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
-	GENERATE_TTF_FILE = OFF;
-	GENERATE_RBF_FILE = ON;
-	GENERATE_HEX_FILE = OFF;
-	SECURITY_BIT = OFF;
-	ENABLE_VREFA_PIN = OFF;
-	ENABLE_VREFB_PIN = OFF;
-	GENERATE_SVF_FILE = OFF;
-	GENERATE_ISC_FILE = OFF;
-	GENERATE_JAM_FILE = OFF;
-	GENERATE_JBC_FILE = OFF;
-	GENERATE_JBC_FILE_COMPRESSED = ON;
-	GENERATE_CONFIG_SVF_FILE = OFF;
-	GENERATE_CONFIG_ISC_FILE = OFF;
-	GENERATE_CONFIG_JAM_FILE = OFF;
-	GENERATE_CONFIG_JBC_FILE = OFF;
-	GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
-	GENERATE_CONFIG_HEXOUT_FILE = OFF;
-	ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
-	BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
-	HEXOUT_FILE_START_ADDRESS = 0;
-	HEXOUT_FILE_COUNT_DIRECTION = UP;
-	RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
-	STRATIX_DEVICE_IO_STANDARD = LVTTL;
-	CLOCK_SOURCE = INTERNAL;
-	CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
-	CONFIGURATION_CLOCK_DIVISOR = 1;
-	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
-	RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	SCLK : LOCATION = Pin_101;
-	SDI : LOCATION = Pin_100;
-	SEN : LOCATION = Pin_98;
-	SLD : LOCATION = Pin_95;
-	adc1_data[0] : LOCATION = Pin_5;
-	adc1_data[10] : LOCATION = Pin_235;
-	adc1_data[11] : LOCATION = Pin_234;
-	adc1_data[1] : LOCATION = Pin_4;
-	adc1_data[2] : LOCATION = Pin_3;
-	adc1_data[3] : LOCATION = Pin_2;
-	adc1_data[4] : LOCATION = Pin_1;
-	adc1_data[4] : IO_STANDARD = LVTTL;
-	adc1_data[5] : LOCATION = Pin_240;
-	adc1_data[6] : LOCATION = Pin_239;
-	adc1_data[7] : LOCATION = Pin_238;
-	adc1_data[8] : LOCATION = Pin_237;
-	adc1_data[9] : LOCATION = Pin_236;
-	adc2_data[0] : LOCATION = Pin_20;
-	adc2_data[10] : LOCATION = Pin_8;
-	adc2_data[11] : LOCATION = Pin_7;
-	adc2_data[1] : LOCATION = Pin_19;
-	adc2_data[2] : LOCATION = Pin_18;
-	adc2_data[3] : LOCATION = Pin_17;
-	adc2_data[4] : LOCATION = Pin_16;
-	adc2_data[5] : LOCATION = Pin_15;
-	adc2_data[6] : LOCATION = Pin_14;
-	adc2_data[7] : LOCATION = Pin_13;
-	adc2_data[8] : LOCATION = Pin_12;
-	adc2_data[9] : LOCATION = Pin_11;
-	adc3_data[0] : LOCATION = Pin_200;
-	adc3_data[10] : LOCATION = Pin_184;
-	adc3_data[11] : LOCATION = Pin_183;
-	adc3_data[1] : LOCATION = Pin_197;
-	adc3_data[2] : LOCATION = Pin_196;
-	adc3_data[3] : LOCATION = Pin_195;
-	adc3_data[4] : LOCATION = Pin_194;
-	adc3_data[5] : LOCATION = Pin_193;
-	adc3_data[6] : LOCATION = Pin_188;
-	adc3_data[7] : LOCATION = Pin_187;
-	adc3_data[8] : LOCATION = Pin_186;
-	adc3_data[9] : LOCATION = Pin_185;
-	adc4_data[0] : LOCATION = Pin_222;
-	adc4_data[10] : LOCATION = Pin_203;
-	adc4_data[11] : LOCATION = Pin_202;
-	adc4_data[1] : LOCATION = Pin_219;
-	adc4_data[2] : LOCATION = Pin_217;
-	adc4_data[3] : LOCATION = Pin_216;
-	adc4_data[4] : LOCATION = Pin_215;
-	adc4_data[5] : LOCATION = Pin_214;
-	adc4_data[6] : LOCATION = Pin_213;
-	adc4_data[7] : LOCATION = Pin_208;
-	adc4_data[8] : LOCATION = Pin_207;
-	adc4_data[9] : LOCATION = Pin_206;
-	adc_oeb[0] : LOCATION = Pin_228;
-	adc_oeb[1] : LOCATION = Pin_21;
-	adc_oeb[2] : LOCATION = Pin_181;
-	adc_oeb[3] : LOCATION = Pin_218;
-	adc_otr[0] : LOCATION = Pin_233;
-	adc_otr[1] : LOCATION = Pin_6;
-	adc_otr[2] : LOCATION = Pin_182;
-	adc_otr[3] : LOCATION = Pin_201;
-	adclk0 : LOCATION = Pin_224;
-	adclk1 : LOCATION = Pin_226;
-	clk0 : LOCATION = Pin_28;
-	clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
-	clk0 : IO_STANDARD = LVTTL;
-	clk1 : LOCATION = Pin_29;
-	clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
-	clk1 : IO_STANDARD = LVTTL;
-	clk3 : LOCATION = Pin_152;
-	clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
-	clk3 : IO_STANDARD = LVTTL;
-	clk_120mhz : LOCATION = Pin_153;
-	clk_120mhz : IO_STANDARD = LVTTL;
-	clk_out : LOCATION = Pin_63;
-	clk_out : IO_STANDARD = LVTTL;
-	dac1_data[0] : LOCATION = Pin_165;
-	dac1_data[10] : LOCATION = Pin_177;
-	dac1_data[11] : LOCATION = Pin_178;
-	dac1_data[12] : LOCATION = Pin_179;
-	dac1_data[13] : LOCATION = Pin_180;
-	dac1_data[1] : LOCATION = Pin_166;
-	dac1_data[2] : LOCATION = Pin_167;
-	dac1_data[3] : LOCATION = Pin_168;
-	dac1_data[4] : LOCATION = Pin_169;
-	dac1_data[5] : LOCATION = Pin_170;
-	dac1_data[6] : LOCATION = Pin_173;
-	dac1_data[7] : LOCATION = Pin_174;
-	dac1_data[8] : LOCATION = Pin_175;
-	dac1_data[9] : LOCATION = Pin_176;
-	dac2_data[0] : LOCATION = Pin_159;
-	dac2_data[10] : LOCATION = Pin_163;
-	dac2_data[11] : LOCATION = Pin_139;
-	dac2_data[12] : LOCATION = Pin_164;
-	dac2_data[13] : LOCATION = Pin_138;
-	dac2_data[1] : LOCATION = Pin_158;
-	dac2_data[2] : LOCATION = Pin_160;
-	dac2_data[3] : LOCATION = Pin_156;
-	dac2_data[4] : LOCATION = Pin_161;
-	dac2_data[5] : LOCATION = Pin_144;
-	dac2_data[6] : LOCATION = Pin_162;
-	dac2_data[7] : LOCATION = Pin_141;
-	dac2_data[8] : LOCATION = Pin_143;
-	dac2_data[9] : LOCATION = Pin_140;
-	dac3_data[0] : LOCATION = Pin_122;
-	dac3_data[10] : LOCATION = Pin_134;
-	dac3_data[11] : LOCATION = Pin_135;
-	dac3_data[12] : LOCATION = Pin_136;
-	dac3_data[13] : LOCATION = Pin_137;
-	dac3_data[1] : LOCATION = Pin_123;
-	dac3_data[2] : LOCATION = Pin_124;
-	dac3_data[3] : LOCATION = Pin_125;
-	dac3_data[4] : LOCATION = Pin_126;
-	dac3_data[5] : LOCATION = Pin_127;
-	dac3_data[6] : LOCATION = Pin_128;
-	dac3_data[7] : LOCATION = Pin_131;
-	dac3_data[8] : LOCATION = Pin_132;
-	dac3_data[9] : LOCATION = Pin_133;
-	dac4_data[0] : LOCATION = Pin_104;
-	dac4_data[10] : LOCATION = Pin_118;
-	dac4_data[11] : LOCATION = Pin_119;
-	dac4_data[12] : LOCATION = Pin_120;
-	dac4_data[13] : LOCATION = Pin_121;
-	dac4_data[1] : LOCATION = Pin_105;
-	dac4_data[2] : LOCATION = Pin_106;
-	dac4_data[3] : LOCATION = Pin_107;
-	dac4_data[4] : LOCATION = Pin_108;
-	dac4_data[5] : LOCATION = Pin_113;
-	dac4_data[6] : LOCATION = Pin_114;
-	dac4_data[7] : LOCATION = Pin_115;
-	dac4_data[8] : LOCATION = Pin_116;
-	dac4_data[9] : LOCATION = Pin_117;
-	enable_rx : LOCATION = Pin_88;
-	enable_tx : LOCATION = Pin_93;
-	gndbus[0] : LOCATION = Pin_223;
-	gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
-	gndbus[0] : IO_STANDARD = LVTTL;
-	gndbus[1] : LOCATION = Pin_225;
-	gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
-	gndbus[1] : IO_STANDARD = LVTTL;
-	gndbus[2] : LOCATION = Pin_227;
-	gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
-	gndbus[2] : IO_STANDARD = LVTTL;
-	gndbus[3] : LOCATION = Pin_62;
-	gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
-	gndbus[3] : IO_STANDARD = LVTTL;
-	gndbus[4] : LOCATION = Pin_64;
-	gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
-	gndbus[4] : IO_STANDARD = LVTTL;
-	misc_pins[0] : LOCATION = Pin_87;
-	misc_pins[0] : IO_STANDARD = LVTTL;
-	misc_pins[10] : LOCATION = Pin_76;
-	misc_pins[10] : IO_STANDARD = LVTTL;
-	misc_pins[11] : LOCATION = Pin_74;
-	misc_pins[11] : IO_STANDARD = LVTTL;
-	misc_pins[1] : LOCATION = Pin_86;
-	misc_pins[1] : IO_STANDARD = LVTTL;
-	misc_pins[2] : LOCATION = Pin_85;
-	misc_pins[2] : IO_STANDARD = LVTTL;
-	misc_pins[3] : LOCATION = Pin_84;
-	misc_pins[3] : IO_STANDARD = LVTTL;
-	misc_pins[4] : LOCATION = Pin_83;
-	misc_pins[4] : IO_STANDARD = LVTTL;
-	misc_pins[5] : LOCATION = Pin_82;
-	misc_pins[5] : IO_STANDARD = LVTTL;
-	misc_pins[6] : LOCATION = Pin_79;
-	misc_pins[6] : IO_STANDARD = LVTTL;
-	misc_pins[7] : LOCATION = Pin_78;
-	misc_pins[7] : IO_STANDARD = LVTTL;
-	misc_pins[8] : LOCATION = Pin_77;
-	misc_pins[8] : IO_STANDARD = LVTTL;
-	misc_pins[9] : LOCATION = Pin_75;
-	misc_pins[9] : IO_STANDARD = LVTTL;
-	reset : LOCATION = Pin_94;
-	usbclk : LOCATION = Pin_55;
-	usbctl[0] : LOCATION = Pin_56;
-	usbctl[1] : LOCATION = Pin_54;
-	usbctl[2] : LOCATION = Pin_53;
-	usbctl[3] : LOCATION = Pin_58;
-	usbctl[4] : LOCATION = Pin_57;
-	usbctl[5] : LOCATION = Pin_44;
-	usbdata[0] : LOCATION = Pin_73;
-	usbdata[10] : LOCATION = Pin_41;
-	usbdata[11] : LOCATION = Pin_39;
-	usbdata[12] : LOCATION = Pin_38;
-	usbdata[12] : IO_STANDARD = LVTTL;
-	usbdata[13] : LOCATION = Pin_37;
-	usbdata[14] : LOCATION = Pin_24;
-	usbdata[15] : LOCATION = Pin_23;
-	usbdata[1] : LOCATION = Pin_68;
-	usbdata[2] : LOCATION = Pin_67;
-	usbdata[3] : LOCATION = Pin_66;
-	usbdata[4] : LOCATION = Pin_65;
-	usbdata[5] : LOCATION = Pin_61;
-	usbdata[6] : LOCATION = Pin_60;
-	usbdata[7] : LOCATION = Pin_59;
-	usbdata[8] : LOCATION = Pin_43;
-	usbdata[9] : LOCATION = Pin_42;
-	usbrdy[0] : LOCATION = Pin_45;
-	usbrdy[1] : LOCATION = Pin_46;
-	usbrdy[2] : LOCATION = Pin_47;
-	usbrdy[3] : LOCATION = Pin_48;
-	usbrdy[4] : LOCATION = Pin_49;
-	usbrdy[5] : LOCATION = Pin_50;
-	clear_status : LOCATION = Pin_99;
-}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf
deleted file mode 100644
index 6a8aaae426..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf
+++ /dev/null
@@ -1,14 +0,0 @@
-SIMULATOR_SETTINGS
-{
-	ESTIMATE_POWER_CONSUMPTION = OFF;
-	GLITCH_INTERVAL = 1NS;
-	GLITCH_DETECTION = OFF;
-	SIMULATION_COVERAGE = ON;
-	CHECK_OUTPUTS = OFF;
-	SETUP_HOLD_DETECTION = OFF;
-	POWER_ESTIMATION_START_TIME = "0 NS";
-	ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
-	SIMULATION_MODE = TIMING;
-	START_TIME = 0NS;
-	USE_COMPILER_SETTINGS = usrp_radar_mono;
-}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf
deleted file mode 100644
index 0649673995..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf
+++ /dev/null
@@ -1,312 +0,0 @@
-DEFAULT_DESIGN_ASSISTANT_SETTINGS
-{
-	HCPY_ALOAD_SIGNALS = OFF;
-	HCPY_VREF_PINS = OFF;
-	HCPY_CAT = OFF;
-	HCPY_ILLEGAL_HC_DEV_PKG = OFF;
-	ACLK_RULE_IMSZER_ADOMAIN = OFF;
-	ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
-	ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
-	ACLK_CAT = OFF;
-	SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
-	SIGNALRACE_CAT = OFF;
-	NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
-	NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
-	NONSYNCHSTRUCT_RULE_DLATCH = OFF;
-	NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
-	NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
-	NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
-	NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
-	NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
-	NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
-	NONSYNCHSTRUCT_CAT = OFF;
-	NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
-	TIMING_RULE_COIN_CLKEDGE = OFF;
-	TIMING_RULE_SHIFT_REG = OFF;
-	TIMING_RULE_HIGH_FANOUTS = OFF;
-	TIMING_CAT = OFF;
-	RESET_RULE_ALL = OFF;
-	RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
-	RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
-	RESET_RULE_REG_ASNYCH = OFF;
-	RESET_RULE_COMB_ASYNCH_RESET = OFF;
-	RESET_RULE_IMSYNCH_EXRESET = OFF;
-	RESET_RULE_UNSYNCH_EXRESET = OFF;
-	RESET_RULE_INPINS_RESETNET = OFF;
-	RESET_CAT = OFF;
-	CLK_RULE_ALL = OFF;
-	CLK_RULE_MIX_EDGES = OFF;
-	CLK_RULE_CLKNET_CLKSPINES = OFF;
-	CLK_RULE_INPINS_CLKNET = OFF;
-	CLK_RULE_GATING_SCHEME = OFF;
-	CLK_RULE_INV_CLOCK = OFF;
-	CLK_RULE_COMB_CLOCK = OFF;
-	CLK_CAT = OFF;
-	HCPY_EXCEED_USER_IO_USAGE = OFF;
-	HCPY_EXCEED_RAM_USAGE = OFF;
-	NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
-	SIGNALRACE_RULE_TRISTATE = OFF;
-	ASSG_RULE_MISSING_TIMING = OFF;
-	ASSG_RULE_MISSING_FMAX = OFF;
-	ASSG_CAT = OFF;
-}
-SYNTHESIS_FITTING_SETTINGS
-{
-	AUTO_SHIFT_REGISTER_RECOGNITION = ON;
-	AUTO_DSP_RECOGNITION = ON;
-	AUTO_RAM_RECOGNITION = ON;
-	REMOVE_DUPLICATE_LOGIC = ON;
-	AUTO_TURBO_BIT = ON;
-	AUTO_MERGE_PLLS = ON;
-	AUTO_OPEN_DRAIN_PINS = ON;
-	AUTO_PARALLEL_EXPANDERS = ON;
-	AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
-	AUTO_FAST_OUTPUT_REGISTERS = OFF;
-	AUTO_FAST_INPUT_REGISTERS = OFF;
-	AUTO_CASCADE_CHAINS = ON;
-	AUTO_CARRY_CHAINS = ON;
-	AUTO_DELAY_CHAINS = ON;
-	MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
-	PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
-	CASCADE_CHAIN_LENGTH = 2;
-	STRATIX_CARRY_CHAIN_LENGTH = 70;
-	MERCURY_CARRY_CHAIN_LENGTH = 48;
-	FLEX10K_CARRY_CHAIN_LENGTH = 32;
-	FLEX6K_CARRY_CHAIN_LENGTH = 32;
-	CARRY_CHAIN_LENGTH = 48;
-	CARRY_OUT_PINS_LCELL_INSERT = ON;
-	NORMAL_LCELL_INSERT = ON;
-	AUTO_LCELL_INSERTION = ON;
-	ALLOW_XOR_GATE_USAGE = ON;
-	AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
-	AUTO_PACKED_REGISTERS = OFF;
-	AUTO_PACKED_REG_CYCLONE = NORMAL;
-	FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
-	FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
-	MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
-	APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
-	MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
-	STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
-	CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
-	FLEX10K_TECHNOLOGY_MAPPER = LUT;
-	FLEX6K_TECHNOLOGY_MAPPER = LUT;
-	MERCURY_TECHNOLOGY_MAPPER = LUT;
-	APEX20K_TECHNOLOGY_MAPPER = LUT;
-	MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
-	STRATIX_TECHNOLOGY_MAPPER = LUT;
-	AUTO_IMPLEMENT_IN_ROM = OFF;
-	AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
-	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
-	AUTO_GLOBAL_OE = ON;
-	AUTO_GLOBAL_CLOCK = ON;
-	USE_LPM_FOR_AHDL_OPERATORS = ON;
-	LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
-	ENABLE_BUS_HOLD_CIRCUITRY = OFF;
-	WEAK_PULL_UP_RESISTOR = OFF;
-	TURBO_BIT = ON;
-	MAX7000_IGNORE_SOFT_BUFFERS = OFF;
-	IGNORE_SOFT_BUFFERS = ON;
-	MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
-	IGNORE_LCELL_BUFFERS = OFF;
-	IGNORE_ROW_GLOBAL_BUFFERS = OFF;
-	IGNORE_GLOBAL_BUFFERS = OFF;
-	IGNORE_CASCADE_BUFFERS = OFF;
-	IGNORE_CARRY_BUFFERS = OFF;
-	REMOVE_DUPLICATE_REGISTERS = ON;
-	REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
-	ALLOW_POWER_UP_DONT_CARE = ON;
-	PCI_IO = OFF;
-	NOT_GATE_PUSH_BACK = ON;
-	SLOW_SLEW_RATE = OFF;
-	DSP_BLOCK_BALANCING = AUTO;
-	STATE_MACHINE_PROCESSING = AUTO;
-}
-DEFAULT_HARDCOPY_SETTINGS
-{
-	HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
-}
-DEFAULT_TIMING_REQUIREMENTS
-{
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	RUN_ALL_TIMING_ANALYSES = ON;
-	IGNORE_CLOCK_SETTINGS = OFF;
-	DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
-	CUT_OFF_IO_PIN_FEEDBACK = ON;
-	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
-	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
-	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
-	DO_MIN_ANALYSIS = ON;
-	DO_MIN_TIMING = OFF;
-	NUMBER_OF_PATHS_TO_REPORT = 200;
-	NUMBER_OF_DESTINATION_TO_REPORT = 10;
-	NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
-	MAX_SCC_SIZE = 50;
-}
-HDL_SETTINGS
-{
-	VERILOG_INPUT_VERSION = VERILOG_2001;
-	ENABLE_IP_DEBUG = OFF;
-	VHDL_INPUT_VERSION = VHDL93;
-	VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
-}
-PROJECT_INFO(usrp_radar_mono)
-{
-	ORIGINAL_QUARTUS_VERSION = 3.0;
-	PROJECT_CREATION_TIME_DATE = "00:14:04  JULY 13, 2003";
-	LAST_QUARTUS_VERSION = 3.0;
-	SHOW_REGISTRATION_MESSAGE = ON;
-	USER_LIBRARIES = "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells";
-}
-THIRD_PARTY_EDA_TOOLS(usrp_radar_mono)
-{
-	EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
-	EDA_SIMULATION_TOOL = "<NONE>";
-	EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
-	EDA_BOARD_DESIGN_TOOL = "<NONE>";
-	EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
-	EDA_RESYNTHESIS_TOOL = "<NONE>";
-}
-EDA_TOOL_SETTINGS(eda_design_synthesis)
-{
-	EDA_INPUT_GND_NAME = GND;
-	EDA_INPUT_VCC_NAME = VCC;
-	EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_INPUT_DATA_FORMAT = EDIF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	RESYNTHESIS_RETIMING = FULL;
-}
-EDA_TOOL_SETTINGS(eda_simulation)
-{
-	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
-	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
-	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
-	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
-	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
-	EDA_FLATTEN_BUSES = OFF;
-	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
-	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	RESYNTHESIS_RETIMING = FULL;
-}
-EDA_TOOL_SETTINGS(eda_timing_analysis)
-{
-	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
-	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
-	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
-	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
-	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
-	EDA_FLATTEN_BUSES = OFF;
-	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
-	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	EDA_LAUNCH_CMD_LINE_TOOL = OFF;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	RESYNTHESIS_RETIMING = FULL;
-}
-EDA_TOOL_SETTINGS(eda_board_design)
-{
-	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
-	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
-	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
-	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
-	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
-	EDA_FLATTEN_BUSES = OFF;
-	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
-	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	RESYNTHESIS_RETIMING = FULL;
-}
-EDA_TOOL_SETTINGS(eda_formal_verification)
-{
-	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
-	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
-	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
-	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
-	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
-	EDA_FLATTEN_BUSES = OFF;
-	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
-	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	RESYNTHESIS_RETIMING = FULL;
-}
-EDA_TOOL_SETTINGS(eda_palace)
-{
-	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
-	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
-	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
-	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
-	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
-	EDA_FLATTEN_BUSES = OFF;
-	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
-	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
-	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
-	EDA_OUTPUT_DATA_FORMAT = NONE;
-	RESYNTHESIS_RETIMING = FULL;
-	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
-	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
-	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
-}
-CLOCK(clk_120mhz)
-{
-	FMAX_REQUIREMENT = "120.0 MHz";
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	DUTY_CYCLE = 50;
-	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
-	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
-	INVERT_BASE_CLOCK = OFF;
-}
-CLOCK(usbclk)
-{
-	FMAX_REQUIREMENT = "48.0 MHz";
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	DUTY_CYCLE = 50;
-	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
-	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
-	INVERT_BASE_CLOCK = OFF;
-}
-CLOCK(SCLK)
-{
-	FMAX_REQUIREMENT = "1.0 MHz";
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	DUTY_CYCLE = 50;
-	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
-	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
-	INVERT_BASE_CLOCK = OFF;
-}
-CLOCK(adclk0)
-{
-	FMAX_REQUIREMENT = "60.0 MHz";
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	DUTY_CYCLE = 50;
-	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
-	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
-	INVERT_BASE_CLOCK = OFF;
-}
-CLOCK(adclk1)
-{
-	FMAX_REQUIREMENT = "60.0 MHz";
-	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
-	DUTY_CYCLE = 50;
-	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
-	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
-	INVERT_BASE_CLOCK = OFF;
-}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf
deleted file mode 100644
index d85239e996..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_radar_mono"
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
deleted file mode 100644
index 9b13989c26..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
+++ /dev/null
@@ -1,402 +0,0 @@
-# Copyright (C) 1991-2007 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#		usrp_radar_mono_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#		assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102"
-set_global_assignment -name DISABLE_DA_RULE H101
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# start CLOCK(SCLK)
-# -----------------
-
-	# Classic Timing Assignments
-	# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# start CLOCK(master_clk)
-# -----------------------
-
-	# Classic Timing Assignments
-	# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# start CLOCK(usbclk)
-# -------------------
-
-	# Classic Timing Assignments
-	# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# -----------------------------
-# start ENTITY(usrp_radar_mono)
-
-	# Classic Timing Assignments
-	# ==========================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(usrp_radar_mono)
-# ---------------------------
-set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
-set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
deleted file mode 100644
index ee8859b1b8..0000000000
Binary files a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf and /dev/null differ
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
deleted file mode 100644
index e5645322b1..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
+++ /dev/null
@@ -1,65 +0,0 @@
-{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" {  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" {  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is connected to a signal of width 7. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is connected to a signal of width 7. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is connected to a signal of width 7. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is connected to a signal of width 7. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a signal of width 4. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage11\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage10\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage9\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage8\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage7\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage6\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage5\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage4\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage3\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage2\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage1\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage0\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 81 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 75 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 72 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is connected to a signal of width 11. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a signal of width 20. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a signal of width 4. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND " "Warning: Reduced register \"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin \"MYSTERY_SIGNAL\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin \"usbrdy\[0\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "usbctl\[0\] " "Warning: No output dependent on input pin \"usbctl\[0\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 48 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info: Pin MYSTERY_SIGNAL has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3 has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin usbrdy\[0\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 79 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 73 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 67 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at serial_io.v(48): object \"write_done\" assigned a value but never read" {  } { { "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
deleted file mode 100644
index 2620a32880..0000000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
+++ /dev/null
@@ -1,213 +0,0 @@
-// -*- verilog -*-
-//
-//  USRP - Universal Software Radio Peripheral
-//
-//  Copyright (C) 2003,2004 Matt Ettus
-//  Copyright (C) 2007 Corgan Enterprises LLC
-//
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
-//
-
-module usrp_radar_mono
-(output MYSTERY_SIGNAL,
- input master_clk,
- input SCLK,
- input SDI,
- inout SDO,
- input SEN_FPGA,
-
- input FX2_1,
- output FX2_2,
- output FX2_3,
- 
- input wire [11:0] rx_a_a,
- input wire [11:0] rx_b_a,
- input wire [11:0] rx_a_b,
- input wire [11:0] rx_b_b,
-
- output wire [13:0] tx_a,
- output wire [13:0] tx_b,
-
- output wire TXSYNC_A,
- output wire TXSYNC_B,
- 
-  // USB interface
- input usbclk,
- input wire [2:0] usbctl,
- output wire [1:0] usbrdy,
- inout [15:0] usbdata,  // NB Careful, inout
-
- // These are the general purpose i/o's that go to the daughterboard slots
- inout wire [15:0] io_tx_a,
- inout wire [15:0] io_tx_b,
- inout wire [15:0] io_rx_a,
- inout wire [15:0] io_rx_b
- );	
-   wire [15:0] debugdata,debugctrl;
-   assign MYSTERY_SIGNAL = 1'b0;
-   
-   wire clk64;
-   
-   // wire WR = usbctl[0];
-   wire RD = usbctl[1];
-   wire OE = usbctl[2];
-
-   wire have_pkt_rdy;
-   assign usbrdy[0] = 1'b0; // have_space;
-   assign usbrdy[1] = have_pkt_rdy;
-
-   wire   tx_underrun, rx_overrun;    
-   wire   clear_status = FX2_1;
-   assign FX2_2 = rx_overrun;
-   assign FX2_3 = 1'b0; // tx_underrun;
-      
-   wire [15:0] usbdata_out;
-   
-   wire [3:0]  rx_numchan;
-   wire        enable_tx, enable_rx;
-   wire        tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
-   
-   // Tri-state bus macro
-   bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
-
-   assign      clk64 = master_clk;
-
-   // TX
-   wire        tx_sample_strobe;
-   wire        io_tx_ena;
-   
-   wire        serial_strobe;
-   wire [6:0]  serial_addr;
-   wire [31:0] serial_data;
-
-   ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-   // Transmit Side
-   
-   wire        tx_side;
-   wire [13:0] tx_i, tx_q;
-   wire [13:0] tx_dac;
-   wire        tx_sync;
-   
-   dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
-		     .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
-		     .tx_data_o(tx_dac),.tx_sync_o(tx_sync));
-
-   // Route transmitted signal to side A or side B
-   assign tx_a = tx_side ? 14'b0 : tx_dac;
-   assign tx_b = tx_side ? tx_dac : 14'b0;
-   assign TXSYNC_A = tx_side ? 1'b0 : tx_sync;
-   assign TXSYNC_B = tx_side ? tx_sync : 1'b0;
-   
-   /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-   // Receive Side
-   wire        rx_strobe;
-   wire [15:0] rx_adc0_i, rx_adc0_q;
-   wire [15:0] rx_buf_i, rx_buf_q;
-   
-   adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
-			       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-			       .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
-			       .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
-			       .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
-			       .ddc1_in_i(),.ddc1_in_q(),
-			       .ddc2_in_i(),.ddc2_in_q(),
-			       .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
-
-   rx_buffer rx_buffer
-     ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
-       .reset_regs(rx_dsp_reset),
-       .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
-       .channels(rx_numchan),
-       .ch_0(rx_buf_i),.ch_1(rx_buf_q),
-       .ch_2(),.ch_3(),
-       .ch_4(),.ch_5(),
-       .ch_6(),.ch_7(),
-       .rxclk(clk64),.rxstrobe(rx_strobe),
-       .clear_status(clear_status),
-       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-       .debugbus() );
-   
-
-   ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-   // Top level application
-   radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
-	     .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
-	     .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
-	     .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.io_tx_ena_o(io_tx_ena)
-	   );
-
-   // Route TX enable out to RFX transmit mixer enable
-   assign io_tx_a[5] = tx_side ? 1'bz : io_tx_ena;
-   assign io_tx_b[5] = tx_side ? io_tx_ena : 1'bz;
-
-   // Route opposite of TX enable out to RFX receive mixer
-   //assign io_rx_a[5] = tx_side ? 1'bz : ~io_tx_ena;
-   //assign io_rx_b[5] = tx_side ? ~io_tx_ena : 1'bz;
-   assign io_rx_a[5] = 1'b1;
-   assign io_rx_b[5] = 1'b1;
-   
-   
-   // Route TX enable out to RX/TX switch
-   assign io_tx_a[6] = tx_side ? 1'bz : ~io_tx_ena;
-   assign io_tx_b[6] = tx_side ? ~io_tx_ena : 1'bz;
-
-   // Enable common RX/TX antenna
-   assign io_rx_a[6] = tx_side ? 1'bz : 1'b0;
-   assign io_rx_b[6] = tx_side ? 1'b0 : 1'bz;
-   
-   ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-   // Control Functions
-
-   wire [31:0] capabilities;
-   assign capabilities[7]   = 0;  // `TX_CAP_HB;
-   assign capabilities[6:4] = 1;  // `TX_CAP_NCHAN;
-   assign capabilities[3]   = 0;  // `RX_CAP_HB;
-   assign capabilities[2:0] = 2;  // `RX_CAP_NCHAN;
-
-   serial_io serial_io
-     ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
-       .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
-       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-       .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
-       .readback_4(),.readback_5(),.readback_6(),.readback_7()
-       );
-
-   wire [15:0] reg_0,reg_1,reg_2,reg_3;
-   master_control master_control
-     ( .master_clk(clk64),.usbclk(usbclk),
-       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
-       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
-       .enable_tx(enable_tx),.enable_rx(enable_rx),
-       .interp_rate(),.decim_rate(),
-       .tx_sample_strobe(),.strobe_interp(),
-       .rx_sample_strobe(),.strobe_decim(),
-       .tx_empty(),
-       .debug_0(),.debug_1(),
-       .debug_2(),.debug_3(),
-       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
-
-   wire [1:0] dummy_io = 2'bz;
-   
-   io_pins io_pins
-     (.io_0({io_tx_a[15:7],dummy_io,io_tx_a[4:0]}), // Don't connect pins used above
-      .io_1({io_rx_a[15:7],dummy_io,io_rx_a[4:0]}),
-      .io_2({io_tx_b[15:7],dummy_io,io_tx_b[4:0]}),
-      .io_3({io_rx_b[15:7],dummy_io,io_rx_b[4:0]}),
-      .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
-      .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
-      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
-   
-endmodule // usrp_radar_mono
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