USRP FPGA
The FPGA being used on the USRP is an Altera Cyclone EP1C12Q240C8.
Features of the EP1C12:
| LEs | 12,060 |
| M4k RAM blocks (128 x 36 bits) | 52 |
| Total RAM bits | 239,616 |
| PLLs | 2 |
| Maximum user I/O pins | 173 |
The hardware language used to describe the functionality within the FPGA is written in Verilog and synthesized using Altera's free web tool Quartus II. It should be noted that Quartus II can run free only within a Windows environment, though there are ways to run Quartus II under Linux without the need for Windows - YMMV.
The FPGA runs off a 64MHz clock with every internal component synchronous to that global clock. Due to the relatively high clocking frequency, everything within the FPGA is highly pipelined to achieve the highest speed possible.
Receive Chain
See UsrpRfxDiagrams.
AD9862 -> CORDIC -> Decimating CIC Filter (4 stage, Programmable decimation rate [4,128]) -> Halfband Decimation Filter (Fixed decimation by 2) -> RX FIFO.
This yields possible decimation rates of all even numbers between [8,256].
Transmit Chain
Here is a rough diagram of the transmit chain:
For a more complete diagram see UsrpRfxDiagrams.
There are two clocks: one for the USB bus (up to the FIFO) and one for the transmit chain itself. Channel 0 has a loop back facility. The Cascaded Integrator Comb (CIC) interpolation filter rate is controlled by the register FR_INTERP_RATE. The CORDIC transformation is currently disabled in svn HEAD.
Link to the way the AD9862 MxFE is controlled and how the filters in that component is controlled.
USB Interface
Describe how the host communicates with the USRP device.
FPGA Registers
Registers are separated out into three different sections - common, standard, and custom. The registers are write only with values shadowed on the host for readback except for three readable standard registers in their own address space from the writable registers.
Common Registers
Writable Address Range: 0 - 31
| Address | Register | Brief Description |
| 0 | FR_TX_SAMPLE_RATE_DIV | Transmit sample rate divisor |
| 1 | FR_RX_SAMPLE_RATE_DIV | Receive sample rate divisor |
| 2 | UNUSED | Unused Register |
| 3 | UNUSED | Unused Register |
| 4 | FR_MASTER_CTRL | Master Reset and Enable controls |
| 5 | FR_OE_0 | IO Buffer direction settings for pins that go to daugherboards |
| 6 | FR_OE_1 | IO Buffer direction settings for pins that go to daugherboards |
| 7 | FR_OE_2 | IO Buffer direction settings for pins that go to daugherboards |
| 8 | FR_OE_3 | IO Buffer direction settings for pins that go to daugherboards |
| 9 | FR_IO_0 | IO Registers for pins that go to daugherboards |
| 10 | FR_IO_1 | IO Registers for pins that go to daugherboards |
| 11 | FR_IO_2 | IO Registers for pins that go to daugherboards |
| 12 | FR_IO_3 | IO Registers for pins that go to daugherboards |
| 13 | FR_MODE | Sets RX Mode [NORMAL,LOOPBACK,RX_COUNTING,RX_COUNTING_32BIT] |
| 14 | FR_DEBUG_EN | Enables debug settings for debugging FPGA designs |
| 15 | FR_DC_OFFSET_CL_EN | DC offset control loop enable |
| 16 | FR_ADC_OFFSET_0 | ADC/DAC DC correction offset value (2's compliment) |
| 17 | FR_ADC_OFFSET_1 | ADC/DAC DC correction offset value (2's compliment) |
| 18 | FR_ADC_OFFSET_2 | ADC/DAC DC correction offset value (2's compliment) |
| 19 | FR_ADC_OFFSET_3 | ADC/DAC DC correction offset value (2's compliment) |
| 20 | FR_ATR_MASK_0 | Automatic Transmit/Receive Enable (Slot 0) |
| 21 | FR_ATR_TXVAL_0 | Automatic Transmit/Receive TX Pin Values (Slot 0) |
| 22 | FR_ATR_RXVAL_0 | Automatic Transmit/Receive RX Pin Values (Slot 0) |
| 23 | FR_ATR_MASK_1 | Automatic Transmit/Receive Enable (Slot 1) |
| 24 | FR_ATR_TXVAL_1 | Automatic Transmit/Receive TX Pin Values (Slot 1) |
| 25 | FR_ATR_RXVAL_1 | Automatic Transmit/Receive RX Pin Values (Slot 1) |
| 26 | FR_ATR_MASK_2 | Automatic Transmit/Receive Enable (Slot 2) |
| 27 | FR_ATR_TXVAL_2 | Automatic Transmit/Receive TX Pin Values (Slot 2) |
| 28 | FR_ATR_RXVAL_2 | Automatic Transmit/Receive RX Pin Values (Slot 2) |
| 29 | FR_ATR_MASK_3 | Automatic Transmit/Receive Enable (Slot 3) |
| 30 | FR_ATR_TXVAL_3 | Automatic Transmit/Receive TX Pin Values (Slot 3) |
| 31 | FR_ATR_RXVAL_3 | Automatic Transmit/Receive RX Pin Values (Slot 3) |
Standard Registers
Writable Address Range: 32 - 63
| Address | Register | Brief Description |
| 32 | FR_INTERP_RATE | Transmit interpolation rate [1,1024] |
| 33 | FR_DECIM_RATE | Receive decimation rate [1,256] |
| 34 | FR_RX_FREQ_0 | DDC Center Frequency (word 0) |
| 35 | FR_RX_FREQ_1 | DDC Center Frequency (word 1) |
| 36 | FR_RX_FREQ_2 | DDC Center Frequency (word 2) |
| 37 | FR_RX_FREQ_3 | DDC Center Frequency (word 3) |
| 38 | FR_RX_MUX | Configure the RX muxing stream of I/Q data |
| 39 | FR_TX_MUX | Configure the TX muxing stream of I/Q data |
| 40 | FR_TX_A_REFCLK | Configures a reference clock sent to daughterboard A (TX) |
| 41 | FR_RX_A_REFCLK | Configures a reference clock sent to daughterboard A (RX) |
| 42 | FR_TX_B_REFCLK | Configures a reference clock sent to daughterboard B (TX) |
| 43 | FR_RX_B_REFCLK | Configures a reference clock sent to daughterboard B (RX) |
| 44 | FR_RX_PHASE_0 | RX DDC Starting Phase (word 0) |
| 45 | FR_RX_PHASE_1 | RX DDC Starting Phase (word 1) |
| 46 | FR_RX_PHASE_2 | RX DDC Starting Phase (word 2) |
| 47 | FR_RX_PHASE_3 | RX DDC Starting Phase (word 3) |
| 48 | FR_TX_FORMAT | Configures TX Format |
| 49 | FR_RX_FORMAT | Configures RX Format |
| 50 | AVAILABLE | Available for future use |
| 51 | AVAILABLE | Available for future use |
| 52 | AVAILABLE | Available for future use |
| 53 | AVAILABLE | Available for future use |
| 54 | AVAILABLE | Available for future use |
| 55 | AVAILABLE | Available for future use |
| 56 | AVAILABLE | Available for future use |
| 57 | AVAILABLE | Available for future use |
| 58 | AVAILABLE | Available for future use |
| 59 | AVAILABLE | Available for future use |
| 60 | AVAILABLE | Available for future use |
| 61 | AVAILABLE | Available for future use |
| 62 | AVAILABLE | Available for future use |
| 63 | AVAILABLE | Available for future use |
Readable Address Range: 1 - 3
There are only three readable registers, and they are in a separate 'address space' from the writable registers. They are defined at the bottom of fpga_regs_standard.h (Search for READBACK Registers.)
| Address | Register | Brief Description |
| 1 | FR_RB_IO_RX_A_IO_TX_A | Readback A-Side I/O pins |
| 2 | FR_RB_IO_RX_B_IO_TX_B | Readback B-Side I/O pins |
| 3 | FR_RB_CAPS | Readback FPGA capabilities |
Custom Registers
Writable Address Range: 64 - 79
These register addresses are guaranteed to never be used within the standard or common definitions and are therefore reserved for custom USRP FPGA implementations.
Daughterboard Control
How to write to the USB interface to control things such as frequency tuning or filtering. Timing diagrams or links to daughterboard specific PLL locking times, synthesizer lock times, etc might be useful here as well as links to different daughterboard pages here on the Wiki.
List of Daughterboards
See List of USRP daughterboards
Message Block
Describe or link to the message block component of the FPGA allowing for tightly timed transmit and receive functionality.
