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AD9862 Codec Questions

• I was looking at the AD9862 data sheet, and it seems that in the transmit path, there is only one 14bit input but the chip outputs 2 TX signals. Does this mean that if we want to output two signals, the data has to be interleaved before being sent to the AD chip? I am not sure why there are 2 outputs but only 1 input?

The data sent to the AD9862 is interleaved, IQIQIQIQIQ.

• I am trying to figure out how the AD9862 MxFE is setup:

RX Side:
1. Is the internal DLL used to sample faster than 64MSPS? If so, what is the DLL rate? Is it possible this would ever want to be used?
2. Is the Hilbert Filter ever used?

TX Side:
1. Is the Hilbert Filter ever used?
2. Is the NCO ever used?
3. Is the interpolation filter ever used?
4. Is the fixed [Fs/4,Fs/8] selectable mixer ever used?
5. Is the TX data ever sent as real-only instead of I/Q from the FPGA when it is actually a complex signal?

Aux Side:
Are any of the auxiliary ADC/DACs used for AGC/VCO setting?


RX Side:
1- The DLL is used to double the sample rate so that the *DACs* can sample at 128MHz. The ADCs stay at 64MHz.
2- No

TX Side:
1- No
2- Yes, all the time (both coarse and fine). In the up converter (in the AD9862, from figure 3 in the 9862 datasheet), they split the complex multiply into 2 parts -- coarse and fine. The fine part (block D) runs at 1/4 of the sample rate. This means that it can only move the freqency 1/4th as far. The block is then followed by the 4x interpolation (Block C), and then the coarse modulation, Block B. Block B only moves the signal +/- fs/4 or fs/8.
3- Yes, always.
4- Yes
5- No, we always send I/Q to the 9862. There are a couple of use cases, where you might want to send real data, but we don't implement them.

Aux:
Yes, all of them. Details depend on the specific daughterboard. The aux DAC/ADC's are all run to the daughterboards.

• How are the AD9862 registers maintained?

The AD9862 is controlled over SPI. The code that sets up the AD9862's is contained in usrp_basic.cc and usrp_standard.cc. Most of it is in the constructors. You may also want to take a look at the USRP motherboard schematic to see how everything is wired together.

• I have two Basic_Tx daughterboards, so each one uses different AD9862. Are the 2 AD9862 both get there clock in from the usrp motherboard, and that is the same clock?

The AD9862s (which are on the motherboard) both get the same clock from AD9513 clock distribution IC. The only difference is that the clock signal goes through separate (but identical) filters on its way to each AD9862.

• Would you please iterate more on the concept of AD9862 PGA?

It's an analog amplifier with a software controllable gain. On the Rx path it has steps of 1.0 dB before ADC. On the TX path, the steps are 0.1 dB after the DAC. See the AD9862 datasheet for details. The PGA is controlled over the SPI serial bus from the FX2 (as are all the AD9862 registers).

• I need a way to update the AUX_DAC port on the 9862, but apparently that is handled by the USB microcontroller! Is that correct? To set up the AUX_DAC do I have to waste USB bandwidth?

The USRP is wired such that only the FX2 can control the AD9862s and you cannot change it from FPGA. However, you can change this hardware wiring by adding R2001, R2004, and R2005 to the USRP. All should be Zero-ohm resistors. Be careful, because you will now have multiple drivers of these nets. You'll need to have the FX2 STOP driving them before you make the FPGA drive them.

This will allow the FPGA to control the AD9862s. You can also make the FPGA control the tuning of the RFX-series daughterboards.

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