Ticket #66 (enhancement)
Opened 2 years ago
Last modified 1 year ago
hw/sw closed loop AGC
Status: new
| Reported by: | eb | Assigned to: | matt |
|---|---|---|---|
| Priority: | normal | Milestone: | to-be-decided |
| Component: | usrp | Version: | 2.8svn |
| Keywords: | Cc: | ||
We need to implement a few types of AGC, and have them run a sufficiently tight control loop. We should accept input from all or any of these inputs:
- RSSI on RFX cards
- Post-ADC / Pre-DDC power levels
- Post DDC power levels
We should control the gain using the strategies implemented in the daughterboard code. I.e., controlling gain on the d'board if possible and/or the AD9862 Rx PGA.
We should also look at implementing these in the FPGA, with the current gain/level reported in-band across the USB.
Change History
10/02/06 12:46:11: Modified by jcorgan
- milestone changed from post-release-3.0 to release-3.2.
10/02/06 16:13:51: Modified by jcorgan
- milestone changed from release-3.2 to to-be-decided.
Milestone release-3.2 deleted
10/14/06 11:28:48: Modified by jcorgan
- milestone changed from to-be-decided to release-3.1.
07/26/07 08:54:31: Modified by jcorgan
- milestone changed from release-3.1 to to-be-decided.
Milestone post-release-3.0 deleted