Changeset 9761

Timestamp:

10/08/08 22:22:38

Author:

eb

Message:

Add support for ATR and REFCLK to usrp_basic.

Files:

• gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc (modified) (8 diffs)
• gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h (modified) (5 diffs)

gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc

@@ -29 +29 @@
-#include "usrp_interfaces.h"
-#include "fpga_regs_common.h"
+#include "fpga_regs_standard.h"
-#include "fusb.h"
-#include <usb.h>
@@ -426 +427 @@
-}
-
+bool
+usrp_basic::write_atr_tx_delay(int value)
+{
+  return _write_fpga_reg(FR_ATR_TX_DELAY, value);
+}
+
+bool
+usrp_basic::write_atr_rx_delay(int value)
+{
+  return _write_fpga_reg(FR_ATR_RX_DELAY, value);
+}
+
-/*
- * ----------------------------------------------------------------
@@ -448 +461 @@
-
-static int
+slot_id_to_refclk_reg(int slot_id)
+{
+  static int reg[4]  = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
+  assert (0 <= slot_id && slot_id < 4);
+  return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_mask_reg(int slot_id)
+{
+  static int reg[4]  = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
+  assert (0 <= slot_id && slot_id < 4);
+  return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_txval_reg(int slot_id)
+{
+  static int reg[4]  = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
+  assert (0 <= slot_id && slot_id < 4);
+  return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_rxval_reg(int slot_id)
+{
+  static int reg[4]  = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
+  assert (0 <= slot_id && slot_id < 4);
+  return reg[slot_id];
+}
+
+static int
-to_slot(txrx_t txrx, int which_side)
-{
@@ -588 +633 @@
-    return READ_FAILED;
-  return value;
+}
+
+bool
+usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
+{
+  if (! (0 <= which_side && which_side <= 1))
+    return false;
+
+  return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
+                         value);
+}
+
+bool
+usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
+{
+  if (! (0 <= which_side && which_side <= 1))
+    return false;
+
+  return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
+                         value);
+}
+
+bool
+usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
+{
+  if (! (0 <= which_side && which_side <= 1))
+    return false;
+
+  return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
+                         value);
+}
+
+bool
+usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
+{
+  if (! (0 <= which_side && which_side <= 1))
+    return false;
+
+  return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
+                         value);
-}
-
@@ -676 +761 @@
-                                           fusb_block_size, fusb_nblocks);
-
-_write_fpga_reg(FR_ATR_MASK_1, 0);   // zero Rx side
-_write_fpga_reg(FR_ATR_TXVAL_1
-_write_fpga_reg(FR_ATR_RXVAL_1
-_write_fpga_reg(FR_ATR_MASK_3, 0);
-_write_fpga_reg(FR_ATR_TXVAL_3
-_write_fpga_reg(FR_ATR_RXVAL_3
+write_atr_mask(0, 0);                // zero Rx A
+write_atr_txval(0
+write_atr_rxval(0
+write_atr_mask(1, 0);                // zero Rx B Auto Transmit/Receive regs
+write_atr_txval(1
+write_atr_rxval(1
-}
-
@@ -932 +1017 @@
-
-bool
+usrp_basic_rx::write_refclk(int which_side, int value)
+{
+  return common_write_refclk(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_mask(int which_side, int value)
+{
+  return common_write_atr_mask(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_txval(int which_side, int value)
+{
+  return common_write_atr_txval(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_rxval(int which_side, int value)
+{
+  return common_write_atr_rxval(C_RX, which_side, value);
+}
+
+bool
-usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
-{
@@ -1038 +1147 @@
-                                           fusb_block_size, fusb_nblocks);
-
-_write_fpga_reg(FR_ATR_MASK_0, 0); // zero Tx side
-_write_fpga_reg(FR_ATR_TXVAL_
-_write_fpga_reg(FR_ATR_RXVAL_
-_write_fpga_reg(FR_ATR_MASK_2, 0);
-_write_fpga_reg(FR_ATR_TXVAL_2
-_write_fpga_reg(FR_ATR_RXVAL_2
+write_atr_mask(0, 0);                // zero Tx A
+write_atr_txval(
+write_atr_rxval(
+write_atr_mask(1, 0);                // zero Tx B Auto Transmit/Receive regs
+write_atr_txval(1
+write_atr_rxval(1
-}
-
@@ -1297 +1406 @@
-
-bool
+usrp_basic_tx::write_refclk(int which_side, int value)
+{
+  return common_write_refclk(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_mask(int which_side, int value)
+{
+  return common_write_atr_mask(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_txval(int which_side, int value)
+{
+  return common_write_atr_txval(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_rxval(int which_side, int value)
+{
+  return common_write_atr_rxval(C_TX, which_side, value);
+}
+
+bool
-usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
-{

gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h

@@ -240 +240 @@
-  virtual int daughterboard_id (int which_side) const = 0;
-
+  /*!
+   * \brief Clock ticks to delay rising of T/R signal
+   * \sa write_atr_mask, write_atr_txval, write_atr_rxval
+   */
+  bool write_atr_tx_delay(int value);
+
+  /*!
+   * \brief Clock ticks to delay falling edge of T/R signal
+   * \sa write_atr_mask, write_atr_txval, write_atr_rxval
+   */
+  bool write_atr_rx_delay(int value);
+
+
-  // ================================================================
-  // Routines to access and control daughterboard specific i/o
@@ -341 +354 @@
-
-  /*!
+   * \brief Write daughterboard refclk config register
+   *
+   * \param txrx        Tx or Rx?
+   * \param which_side  [0,1] which d'board
+   * \param value       value to write into register, see below
+   *
+   * <pre>
+   * Control whether a reference clock is sent to the daughterboards,
+   * and what frequency.  The refclk is sent on d'board i/o pin 0.
+   * 
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-----------------------------------------------+-+------------+
+   *  |             Reserved (Must be zero)           |E|   DIVISOR  |
+   *  +-----------------------------------------------+-+------------+
+   * 
+   *  Bit 7  -- 1 turns on refclk, 0 allows IO use
+   *  Bits 6:0 Divider value
+   * </pre>
+   */
+  bool common_write_refclk(txrx_t txrx, int which_side, int value);
+
+  /*!
+   * \brief Automatic Transmit/Receive switching
+   * <pre>
+   *
+   * If automatic transmit/receive (ATR) switching is enabled in the
+   * FR_ATR_CTL register, the presence or absence of data in the FPGA
+   * transmit fifo selects between two sets of values for each of the 4
+   * banks of daughterboard i/o pins.
+   *
+   * Each daughterboard slot has 3 16-bit registers associated with it:
+   *   FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
+   *
+   * FR_ATR_MASK_{0,1,2,3}: 
+   *
+   *   These registers determine which of the daugherboard i/o pins are
+   *   affected by ATR switching.  If a bit in the mask is set, the
+   *   corresponding i/o bit is controlled by ATR, else it's output
+   *   value comes from the normal i/o pin output register:
+   *   FR_IO_{0,1,2,3}.
+   *
+   * FR_ATR_TXVAL_{0,1,2,3}:
+   * FR_ATR_RXVAL_{0,1,2,3}:
+   *
+   *   If the Tx fifo contains data, then the bits from TXVAL that are
+   *   selected by MASK are output.  Otherwise, the bits from RXVAL that
+   *   are selected by MASK are output.
+   * </pre>
+   */
+  bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
+  bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
+  bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
+
+  /*!
-   * \brief Write auxiliary digital to analog converter.
-   *
@@ -455 +523 @@
-   */
-  virtual int read_io (int which_side) = 0;
+
+  /*!
+   * \brief Write daughterboard refclk config register
+   *
+   * \param which_side  [0,1] which d'board
+   * \param value       value to write into register, see below
+   *
+   * <pre>
+   * Control whether a reference clock is sent to the daughterboards,
+   * and what frequency.  The refclk is sent on d'board i/o pin 0.
+   * 
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-----------------------------------------------+-+------------+
+   *  |             Reserved (Must be zero)           |E|   DIVISOR  |
+   *  +-----------------------------------------------+-+------------+
+   * 
+   *  Bit 7  -- 1 turns on refclk, 0 allows IO use
+   *  Bits 6:0 Divider value
+   * </pre>
+   */
+  virtual bool write_refclk(int which_side, int value) = 0;
+
+  virtual bool write_atr_mask(int which_side, int value) = 0;
+  virtual bool write_atr_txval(int which_side, int value) = 0;
+  virtual bool write_atr_rxval(int which_side, int value) = 0;
-
-  /*!
@@ -703 +797 @@
-  bool read_io (int which_side, int *value);
-  int read_io (int which_side);
+  bool write_refclk(int which_side, int value);
+  bool write_atr_mask(int which_side, int value);
+  bool write_atr_txval(int which_side, int value);
+  bool write_atr_rxval(int which_side, int value);
-
-  bool write_aux_dac (int which_side, int which_dac, int value);
@@ -815 +913 @@
-  bool read_io (int which_side, int *value);
-  int read_io (int which_side);
+  bool write_refclk(int which_side, int value);
+  bool write_atr_mask(int which_side, int value);
+  bool write_atr_txval(int which_side, int value);
+  bool write_atr_rxval(int which_side, int value);
-
-  bool write_aux_dac (int which_side, int which_dac, int value);