Changeset 9748
- Timestamp:
- 10/08/08 01:05:57
- Files:
-
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc (modified) (3 diffs)
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h (modified) (2 diffs)
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc (modified) (3 diffs)
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc (modified) (21 diffs)
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h (modified) (17 diffs)
- gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_standard.cc (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.cc
r9733 r9748 43 43 d_usrp = usrp; 44 44 45 // FIXME: this is a stupid response some the Python examples requiring _which46 _which = which;47 48 45 if(d_tx) { 49 46 d_slot = d_which * 2; … … 300 297 } 301 298 299 #if 0 // FIXME tune shouldn't be a method of db_base 302 300 tune_result 303 301 db_base::tune(int chan, double target_freq) … … 372 370 return res; 373 371 } 372 #endif 373 gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_base.h
r9733 r9748 91 91 virtual void select_rx_antenna(int which_antenna); 92 92 93 tune_result tune(int chan, double target_freq); 93 // FIXME tune shouldn't be a method of db_base 94 // tune_result tune(int chan, double target_freq); 94 95 95 96 int which() { return d_which; } 96 97 int _which;98 97 99 98 protected: … … 102 101 virtual int _refclk_divisor(); 103 102 104 int d_which;105 usrp_basic *d_usrp;106 int d_refclk_reg;107 bool d_tx;108 int d_slot;103 usrp_basic *d_usrp; 104 int d_which; 105 bool d_tx; 106 int d_refclk_reg; 107 int d_slot; 109 108 }; 110 109 gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/db_boards.cc
r9744 r9748 59 59 60 60 case(USRP_DBID_DBS_RX): 61 db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side))); break; 61 db.push_back(db_base_sptr(new db_dbs_rx(usrp, which_side))); 62 break; 62 63 63 64 case(USRP_DBID_TV_RX): … … 184 185 185 186 case(-1): 186 if (usrp->istx()){187 if (dynamic_cast<usrp_basic_tx*>(usrp)){ 187 188 db.push_back(db_base_sptr(new db_basic_tx(usrp, which_side))); 188 189 } … … 195 196 case(-2): 196 197 default: 197 if (usrp->istx()){198 if (dynamic_cast<usrp_basic_tx*>(usrp)){ 198 199 fprintf(stderr, "\n\aWarning: Treating daughterboard with invalid EEPROM contents as if it were a \"Basic Tx.\"\n"); 199 200 fprintf(stderr, "Warning: This is almost certainly wrong... Use appropriate burn-*-eeprom utility.\n\n"); gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.cc
r9743 r9748 181 181 182 182 bool 183 usrp_basic:: write_aux_dac (int slot, int which_dac, int value)183 usrp_basic::_write_aux_dac (int slot, int which_dac, int value) 184 184 { 185 185 return usrp_write_aux_dac (d_udh, slot, which_dac, value); … … 187 187 188 188 bool 189 usrp_basic:: read_aux_adc (int slot, int which_adc, int *value)189 usrp_basic::_read_aux_adc (int slot, int which_adc, int *value) 190 190 { 191 191 return usrp_read_aux_adc (d_udh, slot, which_adc, value); … … 193 193 194 194 int 195 usrp_basic:: read_aux_adc (int slot, int which_adc)195 usrp_basic::_read_aux_adc (int slot, int which_adc) 196 196 { 197 197 int value; 198 if (! read_aux_adc (slot, which_adc, &value))198 if (!_read_aux_adc (slot, which_adc, &value)) 199 199 return READ_FAILED; 200 200 … … 315 315 } 316 316 317 bool 318 usrp_basic::set_dc_offset_cl_enable(int bits, int mask) 319 { 320 return _write_fpga_reg(FR_DC_OFFSET_CL_EN, 321 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask)); 322 } 323 317 324 // ---------------------------------------------------------------- 318 325 … … 418 425 return usrp_set_led (d_udh, which_led, on); 419 426 } 427 428 /* 429 * ---------------------------------------------------------------- 430 * Routines to access and control daughterboard specific i/o 431 * ---------------------------------------------------------------- 432 */ 433 static int 434 slot_id_to_oe_reg (int slot_id) 435 { 436 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 }; 437 assert (0 <= slot_id && slot_id < 4); 438 return reg[slot_id]; 439 } 440 441 static int 442 slot_id_to_io_reg (int slot_id) 443 { 444 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 }; 445 assert (0 <= slot_id && slot_id < 4); 446 return reg[slot_id]; 447 } 448 449 static int 450 to_slot(txrx_t txrx, int which_side) 451 { 452 // TX_A = 0 453 // RX_A = 1 454 // TX_B = 2 455 // RX_B = 3 456 return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX); 457 } 458 459 bool 460 usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain) 461 { 462 if (which_amp < 0 || which_amp > 3) 463 return false; 464 465 gain = std::min(common_pga_max(txrx), 466 std::max(common_pga_min(txrx), gain)); 467 468 int codec = which_amp >> 1; 469 int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx)); 470 471 if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3 472 return _write_9862(codec, REG_TX_PGA, int_gain); 473 } 474 else { 475 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B; 476 477 // read current value to get input buffer bypass flag. 478 unsigned char cur_rx; 479 if (!_read_9862(codec, reg, &cur_rx)) 480 return false; 481 482 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f); 483 return _write_9862(codec, reg, cur_rx); 484 } 485 } 486 487 double 488 usrp_basic::common_pga(txrx_t txrx, int which_amp) const 489 { 490 if (which_amp < 0 || which_amp > 3) 491 return READ_FAILED; 492 493 if (txrx == C_TX){ 494 int codec = which_amp >> 1; 495 unsigned char v; 496 bool ok = _read_9862 (codec, REG_TX_PGA, &v); 497 if (!ok) 498 return READ_FAILED; 499 500 return (pga_db_per_step() * v) + pga_min(); 501 } 502 else { 503 int codec = which_amp >> 1; 504 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B; 505 unsigned char v; 506 bool ok = _read_9862 (codec, reg, &v); 507 if (!ok) 508 return READ_FAILED; 509 510 return (pga_db_per_step() * (v & 0x1f)) + pga_min(); 511 } 512 } 513 514 double 515 usrp_basic::common_pga_min(txrx_t txrx) const 516 { 517 if (txrx == C_TX) 518 return -20.0; 519 else 520 return 0.0; 521 } 522 523 double 524 usrp_basic::common_pga_max(txrx_t txrx) const 525 { 526 if (txrx == C_TX) 527 return 0.0; 528 else 529 return 20.0; 530 } 531 532 double 533 usrp_basic::common_pga_db_per_step(txrx_t txrx) const 534 { 535 if (txrx == C_TX) 536 return 20.0 / 255; 537 else 538 return 20.0 / 20; 539 } 540 541 bool 542 usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask) 543 { 544 if (! (0 <= which_side && which_side <= 1)) 545 return false; 546 547 return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)), 548 (mask << 16) | (value & 0xffff)); 549 } 550 551 bool 552 usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask) 553 { 554 if (! (0 <= which_side && which_side <= 1)) 555 return false; 556 557 return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)), 558 (mask << 16) | (value & 0xffff)); 559 } 560 561 bool 562 usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value) 563 { 564 if (! (0 <= which_side && which_side <= 1)) 565 return false; 566 567 int t; 568 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v) 569 bool ok = _read_fpga_reg(reg, &t); 570 if (!ok) 571 return false; 572 573 if (txrx == C_TX){ 574 *value = t & 0xffff; // FIXME, more magic 575 return true; 576 } 577 else { 578 *value = (t >> 16) & 0xffff; // FIXME, more magic 579 return true; 580 } 581 } 582 583 int 584 usrp_basic::common_read_io(txrx_t txrx, int which_side) 585 { 586 int value; 587 if (!common_read_io(txrx, which_side, &value)) 588 return READ_FAILED; 589 return value; 590 } 591 592 bool 593 usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value) 594 { 595 return _write_aux_dac(to_slot(txrx, which_side), which_dac, value); 596 } 597 598 bool 599 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value) 600 { 601 return _read_aux_adc(to_slot(txrx, which_side), which_adc, value); 602 } 603 604 int 605 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc) 606 { 607 return _read_aux_adc(to_slot(txrx, which_side), which_adc); 608 } 609 420 610 421 611 //////////////////////////////////////////////////////////////// … … 655 845 if (on != rx_enable ()) 656 846 set_rx_enable (on); 657 }658 659 bool660 usrp_basic_rx::set_pga (int which_amp, double gain)661 {662 if (which_amp < 0 || which_amp > 3)663 return false;664 665 gain = std::max (pga_min (), gain);666 gain = std::min (pga_max (), gain);667 668 int codec = which_amp >> 1;669 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;670 671 // read current value to get input buffer bypass flag.672 unsigned char cur_rx;673 if (!_read_9862 (codec, reg, &cur_rx))674 return false;675 676 int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());677 678 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);679 return _write_9862 (codec, reg, cur_rx);680 }681 682 double683 usrp_basic_rx::pga (int which_amp) const684 {685 if (which_amp < 0 || which_amp > 3)686 return READ_FAILED;687 688 int codec = which_amp >> 1;689 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;690 unsigned char v;691 bool ok = _read_9862 (codec, reg, &v);692 if (!ok)693 return READ_FAILED;694 695 return (pga_db_per_step() * (v & 0x1f)) + pga_min();696 }697 698 static int699 slot_id_to_oe_reg (int slot_id)700 {701 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };702 assert (0 <= slot_id && slot_id < 4);703 return reg[slot_id];704 }705 706 static int707 slot_id_to_io_reg (int slot_id)708 {709 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };710 assert (0 <= slot_id && slot_id < 4);711 return reg[slot_id];712 847 } 713 848 … … 761 896 762 897 bool 898 usrp_basic_rx::set_pga (int which_amp, double gain) 899 { 900 return common_set_pga(C_RX, which_amp, gain); 901 } 902 903 double 904 usrp_basic_rx::pga (int which_amp) const 905 { 906 return common_pga(C_RX, which_amp); 907 } 908 909 bool 763 910 usrp_basic_rx::_write_oe (int which_side, int value, int mask) 764 911 { 765 if (! (0 <= which_side && which_side <= 1)) 766 return false; 767 768 return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_side)), 769 (mask << 16) | (value & 0xffff)); 912 return _common_write_oe(C_RX, which_side, value, mask); 770 913 } 771 914 … … 773 916 usrp_basic_rx::write_io (int which_side, int value, int mask) 774 917 { 775 if (! (0 <= which_side && which_side <= 1)) 776 return false; 777 778 return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_side)), 779 (mask << 16) | (value & 0xffff)); 918 return common_write_io(C_RX, which_side, value, mask); 780 919 } 781 920 … … 783 922 usrp_basic_rx::read_io (int which_side, int *value) 784 923 { 785 if (! (0 <= which_side && which_side <= 1)) 786 return false; 787 788 int t; 789 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v) 790 bool ok = _read_fpga_reg (reg, &t); 791 if (!ok) 792 return false; 793 794 *value = (t >> 16) & 0xffff; // FIXME, more magic 795 return true; 924 return common_read_io(C_RX, which_side, value); 796 925 } 797 926 … … 799 928 usrp_basic_rx::read_io (int which_side) 800 929 { 801 int value; 802 if (!read_io (which_side, &value)) 803 return READ_FAILED; 804 return value; 930 return common_read_io(C_RX, which_side); 805 931 } 806 932 … … 808 934 usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value) 809 935 { 810 return usrp_basic::write_aux_dac (dboard_to_slot (which_side), 811 which_dac, value); 936 return common_write_aux_dac(C_RX, which_side, which_dac, value); 812 937 } 813 938 … … 815 940 usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value) 816 941 { 817 return usrp_basic::read_aux_adc (dboard_to_slot (which_side), 818 which_adc, value); 942 return common_read_aux_adc(C_RX, which_side, which_adc, value); 819 943 } 820 944 … … 822 946 usrp_basic_rx::read_aux_adc (int which_side, int which_adc) 823 947 { 824 return usrp_basic::read_aux_adc (dboard_to_slot (which_side), which_adc);948 return common_read_aux_adc(C_RX, which_side, which_adc); 825 949 } 826 950 827 951 int 828 952 usrp_basic_rx::block_size () const { return d_ephandle->block_size(); } 829 830 bool831 usrp_basic_rx::set_dc_offset_cl_enable(int bits, int mask)832 {833 return _write_fpga_reg(FR_DC_OFFSET_CL_EN,834 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));835 }836 953 837 954 //////////////////////////////////////////////////////////////// … … 1093 1210 if (on != tx_enable ()) 1094 1211 set_tx_enable (on); 1095 }1096 1097 bool1098 usrp_basic_tx::set_pga (int which_amp, double gain)1099 {1100 if (which_amp < 0 || which_amp > 3)1101 return false;1102 1103 gain = std::max (pga_min (), gain);1104 gain = std::min (pga_max (), gain);1105 1106 int codec = which_amp >> 1; // 0 and 1 are same, as are 2 and 31107 1108 int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());1109 1110 return _write_9862 (codec, REG_TX_PGA, int_gain);1111 }1112 1113 double1114 usrp_basic_tx::pga (int which_amp) const1115 {1116 if (which_amp < 0 || which_amp > 3)1117 return READ_FAILED;1118 1119 int codec = which_amp >> 1;1120 unsigned char v;1121 bool ok = _read_9862 (codec, REG_TX_PGA, &v);1122 if (!ok)1123 return READ_FAILED;1124 1125 return (pga_db_per_step() * v) + pga_min();1126 1212 } 1127 1213 … … 1175 1261 1176 1262 bool 1263 usrp_basic_tx::set_pga (int which_amp, double gain) 1264 { 1265 return common_set_pga(C_TX, which_amp, gain); 1266 } 1267 1268 double 1269 usrp_basic_tx::pga (int which_amp) const 1270 { 1271 return common_pga(C_TX, which_amp); 1272 } 1273 1274 bool 1177 1275 usrp_basic_tx::_write_oe (int which_side, int value, int mask) 1178 1276 { 1179 if (! (0 <= which_side && which_side <= 1)) 1180 return false; 1181 1182 return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_side)), 1183 (mask << 16) | (value & 0xffff)); 1277 return _common_write_oe(C_TX, which_side, value, mask); 1184 1278 } 1185 1279 … … 1187 1281 usrp_basic_tx::write_io (int which_side, int value, int mask) 1188 1282 { 1189 if (! (0 <= which_side && which_side <= 1)) 1190 return false; 1191 1192 return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_side)), 1193 (mask << 16) | (value & 0xffff)); 1283 return common_write_io(C_TX, which_side, value, mask); 1194 1284 } 1195 1285 … … 1197 1287 usrp_basic_tx::read_io (int which_side, int *value) 1198 1288 { 1199 if (! (0 <= which_side && which_side <= 1)) 1200 return false; 1201 1202 int t; 1203 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v) 1204 bool ok = _read_fpga_reg (reg, &t); 1205 if (!ok) 1206 return false; 1207 1208 *value = t & 0xffff; // FIXME, more magic 1209 return true; 1289 return common_read_io(C_TX, which_side, value); 1210 1290 } 1211 1291 … … 1213 1293 usrp_basic_tx::read_io (int which_side) 1214 1294 { 1215 int value; 1216 if (!read_io (which_side, &value)) 1217 return READ_FAILED; 1218 return value; 1295 return common_read_io(C_TX, which_side); 1219 1296 } 1220 1297 … … 1222 1299 usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value) 1223 1300 { 1224 return usrp_basic::write_aux_dac (dboard_to_slot (which_side), 1225 which_dac, value); 1301 return common_write_aux_dac(C_TX, which_side, which_dac, value); 1226 1302 } 1227 1303 … … 1229 1305 usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value) 1230 1306 { 1231 return usrp_basic::read_aux_adc (dboard_to_slot (which_side), 1232 which_adc, value); 1307 return common_read_aux_adc(C_TX, which_side, which_adc, value); 1233 1308 } 1234 1309 … … 1236 1311 usrp_basic_tx::read_aux_adc (int which_side, int which_adc) 1237 1312 { 1238 return usrp_basic::read_aux_adc (dboard_to_slot (which_side), which_adc);1313 return common_read_aux_adc(C_TX, which_side, which_adc); 1239 1314 } 1240 1315 gnuradio/branches/developers/eb/cppdb-wip/usrp/host/lib/legacy/usrp_basic.h
r9743 r9748 42 42 #include <usrp_slots.h> 43 43 #include <string> 44 #include <boost/shared_ptr.hpp> 45 #include <boost/utility.hpp> 46 47 48 class db_base; 49 typedef boost::shared_ptr<db_base> db_base_sptr; 50 44 51 45 52 struct usb_dev_handle; … … 47 54 class fusb_ephandle; 48 55 56 enum txrx_t { 57 C_RX = 0, 58 C_TX = 1 59 }; 60 61 49 62 /*! 50 63 * \brief base class for usrp operations 51 64 */ 52 class usrp_basic 65 class usrp_basic : boost::noncopyable 53 66 { 54 private:55 // NOT IMPLEMENTED56 usrp_basic (const usrp_basic &rhs); // no copy constructor57 usrp_basic &operator= (const usrp_basic &rhs); // no assignment operator58 59 60 67 protected: 61 68 struct usb_dev_handle *d_udh; … … 93 100 * \returns true iff successful 94 101 */ 95 bool write_aux_dac (int slot, int which_dac, int value);102 bool _write_aux_dac (int slot, int which_dac, int value); 96 103 97 104 /*! … … 103 110 * \returns true iff successful 104 111 */ 105 bool read_aux_adc (int slot, int which_adc, int *value);112 bool _read_aux_adc (int slot, int which_adc, int *value); 106 113 107 114 /*! … … 112 119 * \returns value in the range [0,4095] if successful, else READ_FAILED. 113 120 */ 114 int read_aux_adc (int slot, int which_adc); 121 int _read_aux_adc (int slot, int which_adc); 122 115 123 116 124 public: … … 192 200 bool set_adc_buffer_bypass (int which_adc, bool bypass); 193 201 202 /*! 203 * \brief Enable/disable automatic DC offset removal control loop in FPGA 204 * 205 * \param bits which control loops to enable 206 * \param mask which \p bits to pay attention to 207 * 208 * If the corresponding bit is set, enable the automatic DC 209 * offset correction control loop. 210 * 211 * <pre> 212 * The 4 low bits are significant: 213 * 214 * ADC0 = (1 << 0) 215 * ADC1 = (1 << 1) 216 * ADC2 = (1 << 2) 217 * ADC3 = (1 << 3) 218 * </pre> 219 * 220 * By default the control loop is enabled on all ADC's. 221 */ 222 bool set_dc_offset_cl_enable(int bits, int mask); 194 223 195 224 /*! … … 199 228 */ 200 229 std::string serial_number(); 230 231 /*! 232 * \brief Return daughterboard ID for given side [0,1]. 233 * 234 * \param which_side [0,1] which daughterboard 235 * 236 * \return daughterboard id >= 0 if successful 237 * \return -1 if no daugherboard 238 * \return -2 if invalid EEPROM on daughterboard 239 */ 240 virtual int daughterboard_id (int which_side) const = 0; 241 242 // ================================================================ 243 // Routines to access and control daughterboard specific i/o 244 // 245 // Those with a common_ prefix access either the Tx or Rx side depending 246 // on the txrx parameter. Those without the common_ prefix are virtual 247 // and are overriden in usrp_basic_rx and usrp_basic_tx to access the 248 // the Rx or Tx sides automatically. We provide the common_ versions 249 // for those daughterboards such as the WBX and XCVR2450 that share 250 // h/w resources (such as the LO) between the Tx and Rx sides. 251 252 // ---------------------------------------------------------------- 253 // BEGIN common_ daughterboard control functions 254 255 /*! 256 * \brief Set Programmable Gain Amplifier(PGA) 257 * 258 * \param txrx Tx or Rx? 259 * \param which_amp which amp [0,3] 260 * \param gain_in_db gain value(linear in dB) 261 * 262 * gain is rounded to closest setting supported by hardware. 263 * 264 * \returns true iff sucessful. 265 * 266 * \sa pga_min(), pga_max(), pga_db_per_step() 267 */ 268 bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db); 269 270 /*! 271 * \brief Return programmable gain amplifier gain setting in dB. 272 * 273 * \param txrx Tx or Rx? 274 * \param which_amp which amp [0,3] 275 */ 276 double common_pga(txrx_t txrx, int which_amp) const; 277 278 /*! 279 * \brief Return minimum legal PGA gain in dB. 280 * \param txrx Tx or Rx? 281 */ 282 double common_pga_min(txrx_t txrx) const; 283 284 /*! 285 * \brief Return maximum legal PGA gain in dB. 286 * \param txrx Tx or Rx? 287 */ 288 double common_pga_max(txrx_t txrx) const; 289 290 /*! 291 * \brief Return hardware step size of PGA(linear in dB). 292 * \param txrx Tx or Rx? 293 */ 294 double common_pga_db_per_step(txrx_t txrx) const; 295 296 /*! 297 * \brief Write direction register(output enables) for pins that go to daughterboard. 298 * 299 * \param txrx Tx or Rx? 300 * \param which_side [0,1] which size 301 * \param value value to write into register 302 * \param mask which bits of value to write into reg 303 * 304 * Each d'board has 16-bits of general purpose i/o. 305 * Setting the bit makes it an output from the FPGA to the d'board. 306 * 307 * This register is initialized based on a value stored in the 308 * d'board EEPROM. In general, you shouldn't be using this routine 309 * without a very good reason. Using this method incorrectly will 310 * kill your USRP motherboard and/or daughterboard. 311 */ 312 bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask); 313 314 /*! 315 * \brief Write daughterboard i/o pin value 316 * 317 * \param txrx Tx or Rx? 318 * \param which_side [0,1] which d'board 319 * \param value value to write into register 320 * \param mask which bits of value to write into reg 321 */ 322 bool common_write_io(txrx_t txrx, int which_side, int value, int mask); 323 324 /*! 325 * \brief Read daughterboard i/o pin value 326 * 327 * \param txrx Tx or Rx? 328 * \param which_side [0,1] which d'board 329 * \param value output 330 */ 331 bool common_read_io(txrx_t txrx, int which_side, int *value); 332 333 /*! 334 * \brief Read daughterboard i/o pin value 335 * 336 * \param txrx Tx or Rx? 337 * \param which_side [0,1] which d'board 338 * \returns register value if successful, else READ_FAILED 339 */ 340 int common_read_io(txrx_t txrx, int which_side); 341 342 /*! 343 * \brief Write auxiliary digital to analog converter. 344 * 345 * \param txrx Tx or Rx? 346 * \param which_side [0,1] which d'board 347 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. 348 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. 349 * \param which_dac [2,3] TX slots must use only 2 and 3. 350 * \param value [0,4095] 351 * \returns true iff successful 352 */ 353 bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value); 354 355 /*! 356 * \brief Read auxiliary analog to digital converter. 357 * 358 * \param txrx Tx or Rx? 359 * \param which_side [0,1] which d'board 360 * \param which_adc [0,1] 361 * \param value return 12-bit value [0,4095] 362 * \returns true iff successful 363 */ 364 bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value); 365 366 /*! 367 * \brief Read auxiliary analog to digital converter. 368 * 369 * \param txrx Tx or Rx? 370 * \param which_side [0,1] which d'board 371 * \param which_adc [0,1] 372 * \returns value in the range [0,4095] if successful, else READ_FAILED. 373 */ 374 int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc); 375 376 // END common_ daughterboard control functions 377 // ---------------------------------------------------------------- 378 // BEGIN virtual daughterboard control functions 379 380 /*! 381 * \brief Set Programmable Gain Amplifier (PGA) 382 * 383 * \param which_amp which amp [0,3] 384 * \param gain_in_db gain value (linear in dB) 385 * 386 * gain is rounded to closest setting supported by hardware. 387 * 388 * \returns true iff sucessful. 389 * 390 * \sa pga_min(), pga_max(), pga_db_per_step() 391 */ 392 virtual bool set_pga (int which_amp, double gain_in_db) = 0; 393 394 /*! 395 * \brief Return programmable gain amplifier gain setting in dB. 396 * 397 * \param which_amp which amp [0,3] 398 */ 399 virtual double pga (int which_amp) const = 0; 400 401 /*! 402 * \brief Return minimum legal PGA gain in dB. 403 */ 404 virtual double pga_min () const = 0; 405 406 /*! 407 * \brief Return maximum legal PGA gain in dB. 408 */ 409 virtual double pga_max () const = 0; 410 411 /*! 412 * \brief Return hardware step size of PGA (linear in dB). 413 */ 414 virtual double pga_db_per_step () const = 0; 415 416 /*! 417 * \brief Write direction register (output enables) for pins that go to daughterboard. 418 * 419 * \param which_side [0,1] which size 420 * \param value value to write into register 421 * \param mask which bits of value to write into reg 422 * 423 * Each d'board has 16-bits of general purpose i/o. 424 * Setting the bit makes it an output from the FPGA to the d'board. 425 * 426 * This register is initialized based on a value stored in the 427 * d'board EEPROM. In general, you shouldn't be using this routine 428 * without a very good reason. Using this method incorrectly will 429 * kill your USRP motherboard and/or daughterboard. 430 */ 431 virtual bool _write_oe (int which_side, int value, int mask) = 0; 432 433 /*! 434 * \brief Write daughterboard i/o pin value 435 * 436 * \param which_side [0,1] which d'board 437 * \param value value to write into register 438 * \param mask which bits of value to write into reg 439 */ 440 virtual bool write_io (int which_side, int value, int mask) = 0; 441 442 /*! 443 * \brief Read daughterboard i/o pin value 444 * 445 * \param which_side [0,1] which d'board 446 * \param value output 447 */ 448 virtual bool read_io (int which_side, int *value) = 0; 449 450 /*! 451 * \brief Read daughterboard i/o pin value 452 * 453 * \param which_side [0,1] which d'board 454 * \returns register value if successful, else READ_FAILED 455 */ 456 virtual int read_io (int which_side) = 0; 457 458 /*! 459 * \brief Write auxiliary digital to analog converter. 460 * 461 * \param which_side [0,1] which d'board 462 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. 463 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. 464 * \param which_dac [2,3] TX slots must use only 2 and 3. 465 * \param value [0,4095] 466 * \returns true iff successful 467 */ 468 virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0; 469 470 /*! 471 * \brief Read auxiliary analog to digital converter. 472 * 473 * \param which_side [0,1] which d'board 474 * \param which_adc [0,1] 475 * \param value return 12-bit value [0,4095] 476 * \returns true iff successful 477 */ 478 virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0; 479 480 /*! 481 * \brief Read auxiliary analog to digital converter. 482 * 483 * \param which_side [0,1] which d'board 484 * \param which_adc [0,1] 485 * \returns value in the range [0,4095] if successful, else READ_FAILED. 486 */ 487 virtual int read_aux_adc (int which_side, int which_adc) = 0; 488 489 /*! 490 * \brief returns current fusb block size 491 */ 492 virtual int block_size() const = 0; 493 494 /*! 495 * \brief returns A/D or D/A converter rate in Hz 496 */ 497 virtual long converter_rate() const = 0; 498 499 // END virtual daughterboard control functions 201 500 202 501 // ---------------------------------------------------------------- … … 229 528 */ 230 529 int _read_fpga_reg (int regno); 231 232 530 233 531 /*! … … 347 645 348 646 void probe_rx_slots (bool verbose); 349 int dboard_to_slot (int dboard) { return (dboard << 1) | 1; }350 647 351 648 public: … … 359 656 * Use zero for a reasonable default. 360 657 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default. 658 * \param fpga_filename name of file that contains image to load into FPGA 659 * \param firmware_filename name of file that contains image to load into FX2 361 660 */ 362 661 static usrp_basic_rx *make (int which_board, … … 367 666 ); 368 667 369 // MANIPULATORS370 371 668 /*! 372 669 * \brief tell the fpga the rate rx samples are coming from the A/D's … … 390 687 int read (void *buf, int len, bool *overrun); 391 688 392 // ACCESSORS393 689 394 690 //! sampling rate of A/D converter 395 691 virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M 396 692 long adc_rate() const { return converter_rate(); } 397 long adc_freq() const { return converter_rate(); } //!< deprecated method name398 399 /*!400 * \brief Return daughterboard ID for given Rx daughterboard slot [0,1].401 *402 * \param which_side [0,1] which Rx daughterboard403 *404 * \return daughterboard id >= 0 if successful405 * \return -1 if no daugherboard406 * \return -2 if invalid EEPROM on daughterboard407 */408 693 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; } 409 694 410 // ----------------------------------------------------------------411 // routines for controlling the Programmable Gain Amplifier412 /*!413 * \brief Set Programmable Gain Amplifier (PGA)414 *415 * \param which_amp which A/D [0,3]416 * \param gain_in_db gain value (linear in dB)417 *418 * gain is rounded to closest setting supported by hardware.419 *420 * \returns true iff sucessful.421 *422 * \sa pga_min(), pga_max(), pga_db_per_step()423 */424 695 bool set_pga (int which_amp, double gain_in_db); 425 426 /*!427 * \brief Return programmable gain amplifier gain setting in dB.428 *429 * \param which_amp which A/D [0,3]430 */431 696 double pga (int which_amp) const; 432 433 /*! 434 * \brief Return minimum legal PGA gain in dB. 435 */ 436 double pga_min () const { return 0.0; } 437 438 /*! 439 * \brief Return maximum legal PGA gain in dB. 440 */ 441 double pga_max () const { return 20.0; } 442 443 /*! 444 * \brief Return hardware step size of PGA (linear in dB). 445 */ 446 double pga_db_per_step () const { return 20.0 / 20; } 447 448 /*! 449 * \brief Write direction register (output enables) for pins that go to daughterboard. 450 * 451 * \param which_side [0,1] which d'board 452 * \param value value to write into register 453 * \param mask which bits of value to write into reg 454 * 455 * Each d'board has 16-bits of general purpose i/o. 456 * Setting the bit makes it an output from the FPGA to the d'board. 457 * 458 * This register is initialized based on a value stored in the 459 * d'board EEPROM. In general, you shouldn't be using this routine 460 * without a very good reason. Using this method incorrectly will 461 * kill your USRP motherboard and/or daughterboard. 462 */ 697 double pga_min () const; 698 double pga_max () const; 699 double pga_db_per_step () const; 700 463 701 bool _write_oe (int which_side, int value, int mask); 464 465 /*!466 * \brief Write daughterboard i/o pin value467 *468 * \param which_side [0,1] which d'board469 * \param value value to write into register470 * \param mask which bits of value to write into reg471 */472 702 bool write_io (int which_side, int value, int mask); 473 474 /*!475 * \brief Read daughterboard i/o pin value476 *477 * \param which_side [0,1] which d'board478 * \param value output479 */480 703 bool read_io (int which_side, int *value); 481 482 /*!483 * \brief Read daughterboard i/o pin value484 *485 * \param which_side [0,1] which d'board486 * \returns register value if successful, else READ_FAILED487 */488 704 int read_io (int which_side); 489 705 490 /*!491 * \brief Write auxiliary digital to analog converter.492 *493 * \param which_side [0,1] which d'board494 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.495 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.496 * \param which_dac [2,3] TX slots must use only 2 and 3.497 * \param value [0,4095]498 * \returns true iff successful499 */500 706 bool write_aux_dac (int which_side, int which_dac, int value); 501 502 /*!503 * \brief Read auxiliary analog to digital converter.504 *505 * \param which_side [0,1] which d'board506 * \param which_adc [0,1]507 * \param value return 12-bit value [0,4095]508 * \returns true iff successful509 */510 707 bool read_aux_adc (int which_side, int which_adc, int *value); 511 512 /*! 513 * \brief Read auxiliary analog to digital converter. 514<
