Changeset 9746

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Timestamp:
10/07/08 23:53:22
Author:
matt
Message:

added the basic wb<-->extram interface and a serdes interrupt to tell link status

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  • gnuradio/trunk/usrp2/fpga/serdes/serdes.v

    r9528 r9746  
    1717     output [15:0] tx_occupied, output tx_full, output tx_empty, 
    1818     output [15:0] rx_occupied, output rx_full, output rx_empty, 
     19 
     20     output serdes_link_up, 
    1921      
    2022     output [31:0] debug0,  
    …… 
    4143      .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), 
    4244      .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), 
    43       .debug(debug_rx) ); 
     45      .serdes_link_up(serdes_link_up), .debug(debug_rx) ); 
    4446 
    4547   serdes_fc_tx serdes_fc_tx 

  • gnuradio/trunk/usrp2/fpga/serdes/serdes_rx.v

    r9528 r9746  
    4343 
    4444     output [15:0] fifo_occupied, output fifo_full, output fifo_empty, 
     45     output reg serdes_link_up, 
    4546     output [31:0] debug 
    4647     ); 
    …… 
    337338   assign      wr_dat_o = line_o; 
    338339 
    339    /* 
    340    assign debug = { { fifo_space[15:8] }, 
    341                     { fifo_space[7:0] }, 
    342                     { 2'd0, error_i, sop_i, eop_i, error_o, sop_o, eop_o }, 
    343                     { full, empty, write, read, xfer_active, state[2:0] } }; 
    344  
    345    assign      debug = { { xoff_rcvd,xon_rcvd,sop_i,eop_i,error_i,state[2:0] }, 
    346                          { odd, wait_here, write_pre, write_d, write, full, chosen_data[17:16]}, 
    347                          { chosen_data[15:8] }, 
    348                          { chosen_data[7:0] } }; 
    349    */ 
    350  
     340   wire        slu = ~({2'b11,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}); 
     341   reg [3:0]   slu_reg; 
     342    
     343   always @(posedge clk) 
     344     if(rst) slu_reg <= 0; 
     345     else slu_reg <= {slu_reg[2:0],slu}; 
     346 
     347   always @(posedge clk) 
     348     serdes_link_up <= &slu_reg[3:1]; 
     349    
    351350   assign      debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i, state[2:0] }; 
    352351    

  • gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v

    r9591 r9746  
    44 
    55module u2_core 
    6   #(parameter RAM_SIZE=16384) 
     6  #(parameter RAM_SIZE=32768) 
    77  (// Clocks 
    88   input dsp_clk, 
    …… 
    124124   output RAM_CE1n, 
    125125   output RAM_CENn, 
    126    input RAM_CLK, 
     126   output RAM_CLK, 
    127127   output RAM_WEn, 
    128128   output RAM_OEn, 
    …… 
    157157   wire         ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; 
    158158         
     159   wire         serdes_link_up; 
     160    
    159161   // /////////////////////////////////////////////////////////////////////////////////////////////// 
    160162   // Wishbone Single Master INTERCON 
    161    parameter  dw = 32;  // Data bus width 
    162    parameter  aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space 
    163    parameter sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.   
     163   localparam         dw = 32;  // Data bus width 
     164   localparam         aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space 
     165   localparam sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.   
    164166    
    165167   wire [dw-1:0] m0_dat_o, m0_dat_i; 
    …… 
    167169                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, 
    168170                 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, 
    169                  s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o; 
    170    wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr; 
    171    wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel; 
    172    wire          m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack; 
    173    wire          m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb; 
    174    wire          m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc; 
    175    wire          m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err; 
    176    wire          m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty; 
    177    wire          m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we; 
     171                 s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; 
     172   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; 
     173   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; 
     174   wire          m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; 
     175   wire          m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; 
     176   wire          m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; 
     177   wire          m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; 
     178   wire          m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; 
     179   wire          m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; 
    178180    
    179181   wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), 
    …… 
    214216      .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), 
    215217      .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), 
    216       .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0), 
     218      .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), 
     219      .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), 
    217220      .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  ); 
    218221    
    …… 
    477480   // Interrupt Controller, Slave #8 
    478481 
    479    wire [8:0]   irq={{6'b0,uart_tx_int, uart_rx_int}, 
     482   wire [15:0]          irq={{5'b0, serdes_link_up, uart_tx_int, uart_rx_int}, 
    480483                      {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; 
    481484    
    482    simple_pic #(.is(9),.dwidth(32)) simple_pic 
     485   simple_pic #(.is(16),.dwidth(32)) simple_pic 
    483486     (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), 
    484487      .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), 
    …… 
    606609      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), 
    607610      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), 
    608       .debug0(debug_serdes0), .debug1(debug_serdes1) ); 
     611      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); 
    609612 
    610613   // /////////////////////////////////////////////////////////////////////////////////// 
    611614   // External RAM Interface 
    612615 
    613    extram_interface extram_interface 
    614      (.clk(dsp_clk),.rst(dsp_rst), 
    615       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 
    616       .rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error), 
    617       .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop), 
    618       .wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error), 
    619       .wr_ready_i(wr3_ready),.wr_full_i(wr3_full), 
    620       .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn), 
    621       .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn) ); 
    622  
    623    
     616   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes 
     617 
     618   wire [15:0] bus2ram, ram2bus; 
     619   wire [15:0] bridge_adr; 
     620   wire [1:0]  bridge_sel; 
     621   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack; 
     622    
     623   wire [19:0] page; 
     624   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; 
     625   setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), 
     626                                       .in(set_data),.out(page),.changed()); 
     627 
     628   wb_bridge_16_32 bridge 
     629     (.wb_clk(wb_clk),.wb_rst(wb_rst), 
     630      .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), 
     631      .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), 
     632      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), 
     633      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); 
     634 
     635   wb_zbt16_b wb_zbt16_b 
     636     (.clk(wb_clk),.rst(wb_rst), 
     637      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), 
     638      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), 
     639      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), 
     640      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), 
     641      .sram_mode(),.sram_zz() ); 
     642 
     643   assign      s14_err = 0; assign s14_rty = 0; 
     644   assign      RAM_CE1n = 0; 
     645   assign      RAM_D[17:16] = 2'bzz; 
     646    
    624647   // ///////////////////////////////////////////////////////////////////////////////////////// 
    625648   // Debug Pins 

  • gnuradio/trunk/usrp2/fpga/top/u2_rev3/Makefile

    r9555 r9746  
    9090control_lib/sd_spi.v \ 
    9191control_lib/sd_spi_wb.v \ 
     92control_lib/wb_bridge_16_32.v \ 
    9293coregen/fifo_xlnx_2Kx36_2clk.v \ 
    9394coregen/fifo_xlnx_2Kx36_2clk.xco \ 
    …… 
    121122eth/rtl/verilog/miim/eth_outputcontrol.v \ 
    122123eth/rtl/verilog/miim/eth_shiftreg.v \ 
     124extram/wb_zbt16_b.v \ 
    123125opencores/8b10b/decode_8b10b.v \ 
    124126opencores/8b10b/encode_8b10b.v \