Changeset 9500

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Timestamp:
09/04/08 22:37:20
Author:
eb
Message:

cleaned up SERDES loopback test code

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  • usrp2/trunk/firmware/apps/sd_bounce.c

    r8521 r9500  
    1414 * You should have received a copy of the GNU General Public License 
    1515 * along with this program.  If not, see <http://www.gnu.org/licenses/>. 
     16 */ 
     17 
     18/*  
     19 * Loopback SERDES to SERDES 
    1620 */ 
    1721 
    …… 
    3236#include <stdlib.h> 
    3337#include <string.h> 
    34 #include <ad9510.h> 
     38#include <clocks.h> 
     39 
    3540 
    3641 
    …… 
    6772// ---------------------------------------------------------------- 
    6873 
     74#if 0 
    6975static bool 
    7076check_packet(int *buf, int nlines) 
    …… 
    8793  memset_wa(buffer_ram(bufno), 0, BP_NLINES * 4); 
    8894} 
     95#endif 
    8996 
    9097 
    …… 
    94101  hal_toggle_leds(0x2); 
    95102 
     103#if 0 
    96104  int last_line = buffer_pool_status->last_line[buf_this]; 
    97  
    98   /* 
    99105  bool ok = check_packet(buffer_ram(buf_this), last_line); 
    100106  static int good = 0; 
    …… 
    111117    bad = 0; 
    112118  } 
    113   */ 
     119#endif 
     120 
    114121  return false; 
    115122} 
    …… 
    129136  u2_init(); 
    130137 
     138  putstr("\nsd_bounce\n"); 
     139 
    131140  // Get our clock from the mimo interface 
     141  clocks_mimo_config(MC_WE_LOCK_TO_MIMO); 
    132142 
    133   // if(I WANT TO LOCK TO A REFERENCE CLOCK)  
    134   // Reg 8, Charge pump on, dig lock det, positive PFD, 47 
    135   //ad9510_write_reg(0x08, 0x47); 
    136   //ad9510_write_reg(0x5A, 0x01); // Update Regs 
    137   // if (LOCK_TO_MIMO_REF) 
    138  
    139   // Turn on ref output and choose the MIMO connector 
    140   output_regs->clk_ctrl = 0x15; 
    141   // Turn on ref output and choose the SMA connector 
    142   //output_regs->clk_ctrl = 0x14; 
    143  
    144   // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output 
    145   //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); 
    146   //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); 
    147  
    148   putstr("\nsd_bounce\n"); 
    149    
    150   // Set up serdes 
    151   //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN | SERDES_LOOPEN); 
    152   output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN); 
    153  
    154    
    155143  dbsm_init(&sd_sm, SERDES_RX_BUF_0, 
    156144            &sd_recv_args, &sd_send_args, 

  • usrp2/trunk/firmware/apps/sd_gentest.c

    r8521 r9500  
    3131#include <stdlib.h> 
    3232#include <string.h> 
    33 #include <ad9510.h> 
     33#include <clocks.h> 
    3434#include <mdelay.h> 
    3535 
    …… 
    101101  u2_init(); 
    102102 
    103  
    104   // Reg 8, Charge pump on, dig lock det, positive PFD, 47 
    105   //ad9510_write_reg(0x08, 0x47); 
    106   // turn on ref input and choose the SMA 
    107   //output_regs->clk_ctrl = 0x14;  
    108  
    109   // provide a clock for the serdes (THEY_LOCK_TO_ME) 
    110   ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal levels 
    111   ad9510_write_reg(0x4D, 0x00); // Turn on Div2 
    112   ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock 
    113   ad9510_write_reg(0x5A, 0x01); // Update Regs 
     103  // We're free running and provide clock to the MIMO interface 
     104  clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO); 
    114105 
    115106 
    116107  // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output 
    117   //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); 
    118   //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); 
     108  // output_regs->debug_mux_ctrl = 1; 
     109  // hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); 
     110  // hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); 
    119111 
    120112  putstr("\nsd_gentest\n"); 
    121113   
    122   // Set up serdes 
     114  // Set up serdes (already enabled) 
    123115  //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN | SERDES_LOOPEN); 
    124   output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN); 
     116  //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN); 
    125117 
    126118  init_packets(); 
    …… 
    140132  int ready_to_send = 0; 
    141133 
    142   int counter = 0; 
     134  int counter __attribute__((unused)) = 0; 
    143135  int sent = 1; 
    144136  int txerr = 0; 
    …… 
    236228    if(sent_acc >=10000) { 
    237229      printf("\nOverall\tSENT %d\tTXERR %d\t",sent_acc,txerr_acc); 
    238       printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n",rcvd_acc, rxerr_acc, rxcrc_acc, sent_acc-rcvd_acc); 
     230      printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n\n",rcvd_acc, rxerr_acc, rxcrc_acc, sent_acc-rcvd_acc); 
    239231      sent_acc = 0; 
    240232      txerr_acc = 0; 
    …… 
    274266  } 
    275267   
    276   return 1; 
    277 } 
     268  return 0; 
     269}