Changeset 9150

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Timestamp:
08/01/08 20:01:13
Author:
eb
Message:

work-in-progress

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  • usrp2/trunk/firmware/apps

    • Property svn:ignore changed from *-stamp *.a *.bin *.dump *.log *.rom *.map .deps Makefile Makefile.in aclocal.m4 autom4te.cache blink_leds blink_leds2 build compile config.h config.h.in config.log config.status configure depcomp echo eth_test gen_eth_packets ibs_rx_test ibs_tx_test install-sh libtool ltmain.sh missing py-compile rcv_eth_packets run_tests.sh stamp-h1 test1 test_phy_comm timer_test buf_ram_test buf_ram_zero hello test_printf test_spi test_i2c gen_pause_frames test_serdes rx_only tx_only tx_standalone tx_drop tx_drop2 tx_drop_rate_limited test_lsdac test_lsadc read_dbids test_db_spi ramp_lsdac eth_to_serdes serdes_to_dsp sd_gentest sd_bounce can_i_sub tx_only_v2 rx_only_v2 txrx to *-stamp *.a *.bin *.dump *.log *.rom *.map .deps Makefile Makefile.in aclocal.m4 autom4te.cache blink_leds blink_leds2 build compile config.h config.h.in config.log config.status configure depcomp echo eth_test gen_eth_packets ibs_rx_test ibs_tx_test install-sh libtool ltmain.sh missing py-compile rcv_eth_packets run_tests.sh stamp-h1 test1 test_phy_comm timer_test buf_ram_test buf_ram_zero hello test_printf test_spi test_i2c gen_pause_frames test_serdes rx_only tx_only tx_standalone tx_drop tx_drop2 tx_drop_rate_limited test_lsdac test_lsadc read_dbids test_db_spi ramp_lsdac eth_to_serdes serdes_to_dsp sd_gentest sd_bounce can_i_sub tx_only_v2 rx_only_v2 txrx eth_serdes serdes_txrx
  • usrp2/trunk/firmware/apps/Makefile.am

    r9142 r9150  
    2626        can_i_sub \ 
    2727        echo \ 
     28        eth_serdes \ 
    2829        gen_eth_packets \ 
    2930        hello \ 
     
    4445        tx_standalone \ 
    4546        txrx \ 
     47        serdes_txrx \ 
    4648        sd_gentest \ 
    4749        sd_bounce 
     
    5456tx_only_v2_SOURCES = tx_only_v2.c app_common_v2.c 
    5557txrx_SOURCES = txrx.c app_common_v2.c 
    56 #eth_to_serdes_SOURCES = eth_to_serdes.c app_passthru.c 
    57 #serdes_to_dsp_SOURCES = serdes_to_dsp.c app_common.c 
     58eth_serdes_SOURCES = eth_serdes.c app_passthru_v2.c 
     59serdes_txrx_SOURCES = serdes_txrx.c app_common_v2.c 
    5860 
    59  
    60  
  • usrp2/trunk/firmware/apps/app_common_v2.c

    r9142 r9150  
    3232 
    3333volatile bool link_is_up = false;       // eth handler sets this 
    34  
     34int cpu_tx_buf_dest_port = PORT_ETH; 
    3535 
    3636// If this is non-zero, this dbsm could be writing to the ethernet 
     
    8888  } 
    8989 
     90  if (1){ 
     91    printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, reply_len); 
     92    print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4); 
     93  } 
     94 
    9095  // fire it off 
    91   bp_send_from_buf(CPU_TX_BUF, PORT_ETH, 1, 0, reply_len/4); 
     96  bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4); 
    9297 
    9398  // wait for it to complete (not long, it's a small pkt) 
  • usrp2/trunk/firmware/apps/app_common_v2.h

    r9142 r9150  
    3434extern volatile bool link_is_up;        // eth handler sets this 
    3535 
    36  
    3736// If there's a dbsm that sends to the ethernet, put it's address here 
    3837extern dbsm_t *ac_could_be_sending_to_eth; 
    3938 
     39extern int cpu_tx_buf_dest_port; 
    4040 
    4141void set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt); 
  • usrp2/trunk/firmware/apps/app_passthru_v2.c

    r9144 r9150  
    2121#endif 
    2222 
    23 #include "app_common_v2.h" 
     23#include "app_passthru_v2.h" 
    2424#include "buffer_pool.h" 
    2525#include "memcpy_wa.h" 
     
    3737dbsm_t *ac_could_be_sending_to_eth; 
    3838 
    39 static unsigned char exp_seqno = 0; 
    40  
    41  
    42 static bool 
    43 burn_mac_addr(const op_burn_mac_addr_t *p) 
    44 
    45   return ethernet_set_mac_addr(&p->addr); 
    46 
    47  
    48 static bool 
    49 config_mimo_cmd(const op_config_mimo_t *p) 
    50 
    51   clocks_mimo_config(p->flags); 
    52   return true; 
    53 
     39//static unsigned char exp_seqno = 0; 
    5440 
    5541void 
     
    122108} 
    123109 
    124  
    125 static size_t 
    126 config_tx_v2_cmd(const op_config_tx_v2_t *p, 
    127                  void *reply_payload, size_t reply_payload_space) 
    128 { 
    129   op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload; 
    130   if (reply_payload_space < sizeof(*r)) 
    131     return 0;                                   // no room 
    132  
    133   struct tune_result    tune_result; 
    134   memset(&tune_result, 0, sizeof(tune_result)); 
    135  
    136   bool ok = true; 
    137    
    138   if (p->valid & CFGV_GAIN){ 
    139     ok &= db_set_gain(tx_dboard, p->gain); 
    140   } 
    141  
    142   if (p->valid & CFGV_FREQ){ 
    143     u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo); 
    144     bool tune_ok = db_tune(tx_dboard, f, &tune_result); 
    145     ok &= tune_ok; 
    146     print_tune_result("Tx", tune_ok, f, &tune_result); 
    147   } 
    148  
    149   if (p->valid & CFGV_INTERP_DECIM){ 
    150     int interp = p->interp; 
    151     int hb1 = 0; 
    152     int hb2 = 0; 
    153  
    154     if (!(interp & 1)){ 
    155       hb2 = 1; 
    156       interp = interp >> 1; 
    157     } 
    158  
    159     if (!(interp & 1)){ 
    160       hb1 = 1; 
    161       interp = interp >> 1; 
    162     } 
    163      
    164     if (p->interp < MIN_INTERP || p->interp > MAX_INTERP) 
    165       ok = false; 
    166     else { 
    167       dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp; 
    168       // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp); 
    169     } 
    170   } 
    171  
    172   if (p->valid & CFGV_SCALE_IQ){ 
    173     dsp_tx_regs->scale_iq = p->scale_iq; 
    174   } 
    175  
    176   // Build reply subpacket 
    177  
    178   r->opcode = OP_CONFIG_TX_REPLY_V2; 
    179   r->len = sizeof(*r); 
    180   r->rid = p->rid; 
    181   r->ok = ok; 
    182   r->inverted = tune_result.inverted; 
    183   r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq); 
    184   r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq); 
    185   r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq); 
    186   r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq); 
    187   r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq); 
    188   r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq); 
    189   return r->len; 
    190 } 
    191  
    192 static size_t 
    193 config_rx_v2_cmd(const op_config_rx_v2_t *p,  
    194                  void *reply_payload, size_t reply_payload_space) 
    195 { 
    196   op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload; 
    197   if (reply_payload_space < sizeof(*r)) 
    198     return 0;                           // no room 
    199  
    200   struct tune_result    tune_result; 
    201   memset(&tune_result, 0, sizeof(tune_result)); 
    202  
    203   bool ok = true; 
    204    
    205   if (p->valid & CFGV_GAIN){ 
    206     ok &= db_set_gain(rx_dboard, p->gain); 
    207   } 
    208  
    209   if (p->valid & CFGV_FREQ){ 
    210     u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo); 
    211     bool tune_ok = db_tune(rx_dboard, f, &tune_result); 
    212     ok &= tune_ok; 
    213     print_tune_result("Rx", tune_ok, f, &tune_result); 
    214   } 
    215  
    216   if (p->valid & CFGV_INTERP_DECIM){ 
    217     int decim = p->decim; 
    218     int hb1 = 0; 
    219     int hb2 = 0; 
    220      
    221     if(!(decim & 1)) { 
    222       hb2 = 1; 
    223       decim = decim >> 1; 
    224     } 
    225      
    226     if(!(decim & 1)) { 
    227       hb1 = 1; 
    228       decim = decim >> 1; 
    229     } 
    230      
    231     if (decim < MIN_DECIM || decim > MAX_DECIM) 
    232       ok = false; 
    233     else { 
    234       dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim; 
    235       // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim); 
    236     } 
    237   } 
    238  
    239   if (p->valid & CFGV_SCALE_IQ){ 
    240     dsp_rx_regs->scale_iq = p->scale_iq; 
    241   } 
    242  
    243   // Build reply subpacket 
    244  
    245   r->opcode = OP_CONFIG_RX_REPLY_V2; 
    246   r->len = sizeof(*r); 
    247   r->rid = p->rid; 
    248   r->ok = ok; 
    249   r->inverted = tune_result.inverted; 
    250   r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq); 
    251   r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq); 
    252   r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq); 
    253   r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq); 
    254   r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq); 
    255   r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq); 
    256  
    257   return r->len; 
    258 } 
    259  
    260 static size_t 
    261 read_time_cmd(const op_generic_t *p, 
    262               void *reply_payload, size_t reply_payload_space) 
    263 { 
    264   op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload; 
    265   if (reply_payload_space < sizeof(*r))          
    266     return 0;                                   // no room 
    267  
    268   r->opcode = OP_READ_TIME_REPLY; 
    269   r->len = sizeof(*r); 
    270   r->rid = p->rid; 
    271   r->time = timer_regs->time; 
    272  
    273   return r->len; 
    274 } 
    275  
    276 static size_t 
    277 generic_reply(const op_generic_t *p, 
    278               void *reply_payload, size_t reply_payload_space, 
    279               bool ok) 
    280 { 
    281   op_generic_t *r = (op_generic_t *) reply_payload; 
    282   if (reply_payload_space < sizeof(*r))          
    283     return 0;                                   // no room 
    284  
    285   r->opcode = p->opcode | OP_REPLY_BIT; 
    286   r->len = sizeof(*r); 
    287   r->rid = p->rid; 
    288   r->ok = ok; 
    289  
    290   return r->len; 
    291 } 
    292  
    293110static size_t 
    294111add_eop(void *reply_payload, size_t reply_payload_space) 
     
    306123} 
    307124 
    308 void 
     125bool 
    309126handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len) 
    310127{ 
     
    313130  int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t); 
    314131 
     132  bool handled_it = false; 
     133 
    315134  // initialize reply 
    316135  memset(reply, 0, sizeof(reply)); 
     
    333152    case OP_ID: 
    334153      subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space); 
    335       break; 
    336      
    337     case OP_CONFIG_TX_V2: 
    338       subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload, 
    339                                    reply_payload, reply_payload_space); 
    340       break; 
    341  
    342     case OP_CONFIG_RX_V2: 
    343       subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload, 
    344                                    reply_payload, reply_payload_space); 
    345       break; 
    346  
    347     case OP_START_RX_STREAMING: 
    348       start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload); 
    349       subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true); 
    350       break; 
    351      
    352     case OP_STOP_RX: 
    353       stop_rx_cmd(); 
    354       subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true); 
    355       break; 
    356      
    357     case OP_BURN_MAC_ADDR: 
    358       subpktlen = generic_reply(gp, reply_payload, reply_payload_space, 
    359                                 burn_mac_addr((op_burn_mac_addr_t *) payload)); 
    360       break; 
    361  
    362     case OP_CONFIG_MIMO: 
    363       subpktlen = generic_reply(gp, reply_payload, reply_payload_space, 
    364                                 config_mimo_cmd((op_config_mimo_t *) payload)); 
    365       break; 
    366  
    367     case OP_READ_TIME: 
    368       subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space); 
    369       break; 
    370  
    371     default: 
    372       printf("app_common_v2: unhandled opcode = %d\n", gp->opcode); 
     154      handled_it = true; 
    373155      break; 
    374156    } 
     
    392174 
    393175  send_reply(reply, reply_payload - reply); 
     176 
     177  return handled_it; 
    394178} 
    395179 
     
    419203  switch (chan){ 
    420204  case CONTROL_CHAN: 
    421     handle_control_chan_frame(pkt, byte_len); 
    422     return true;        // we handled the packet 
     205    return handle_control_chan_frame(pkt, byte_len); 
    423206    break; 
    424207 
     
    458241  printf("\neth link changed: speed = %d\n", speed); 
    459242} 
    460  
    461  
    462 void 
    463 print_tune_result(char *msg, bool tune_ok, 
    464                   u2_fxpt_freq_t target_freq, struct tune_result *r) 
    465 { 
    466   printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false"); 
    467   putstr("  target_freq   "); print_fxpt_freq(target_freq); newline(); 
    468   putstr("  baseband_freq "); print_fxpt_freq(r->baseband_freq); newline(); 
    469   putstr("  dxc_freq      "); print_fxpt_freq(r->dxc_freq); newline(); 
    470   putstr("  residual_freq "); print_fxpt_freq(r->residual_freq); newline(); 
    471   printf("  inverted      %s\n", r->inverted ? "true" : "false"); 
    472 } 
  • usrp2/trunk/firmware/apps/app_passthru_v2.h

    r9144 r9150  
    5050void link_changed_callback(int speed); 
    5151 
    52 void 
    53 print_tune_result(char *msg, bool tune_ok, 
    54                   u2_fxpt_freq_t target_freq, struct tune_result *r); 
    55  
    56  
    57 void start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p); 
    58 void stop_rx_cmd(void); 
    59  
    60 void handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len); 
     52bool handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len); 
    6153 
    6254#endif /* INCLUDED_APP_COMMON_H */ 
  • usrp2/trunk/firmware/apps/eth_serdes.c

    r9144 r9150  
    3131#include "usrp2_eth_packet.h" 
    3232#include "dbsm.h" 
    33 #include "app_common_v2.h" 
     33#include "app_passthru_v2.h" 
    3434#include "memcpy_wa.h" 
     35#include "clocks.h" 
    3536#include <stddef.h> 
    3637#include <stdlib.h> 
     
    4647 
    4748/* 
    48  * Full duplex Tx and Rx between ethernet and DSP pipelines 
     49 * Full duplex Tx and Rx between ethernet and serdes 
    4950 * 
    5051 * Buffer 1 is used by the cpu to send frames to the host. 
     
    5455//#define CPU_RX_BUF    0       // eth -> cpu 
    5556 
    56 #define DSP_RX_BUF_0    2       // dsp rx -> eth (double buffer) 
    57 #define DSP_RX_BUF_1    3       // dsp rx -> eth 
    58 #define DSP_TX_BUF_0    4       // eth -> dsp tx (double buffer) 
    59 #define DSP_TX_BUF_1    5       // eth -> dsp tx 
     57#define DSP_RX_BUF_0    2       // serdes -> eth (double buffer) 
     58#define DSP_RX_BUF_1    3       // serdes -> eth 
     59#define DSP_TX_BUF_0    4       // eth -> serdes (double buffer) 
     60#define DSP_TX_BUF_1    5       // eth -> serdes 
    6061 
    6162/* 
    6263 * ================================================================ 
    63  *   configure DSP TX double buffering state machine (eth -> dsp
     64 *   configure serdes double buffering state machine (eth -> serdes
    6465 * ================================================================ 
    6566 */ 
    6667 
    67 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp) 
    68 // DSP Tx reads word0 (flags) + timestamp followed by samples 
    69  
    70 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) 
    7168 
    7269// Receive from ethernet 
     
    7774}; 
    7875 
    79 // send to DSP Tx 
     76// send to serdes 
    8077buf_cmd_args_t dsp_tx_send_args = { 
    81   PORT_DSP
    82   DSP_TX_FIRST_LINE,   // starts just past transport header 
     78  PORT_SERDES
     79  0, 
    8380  0                     // filled in from last_line register 
    8481}; 
     
    8784 
    8885/* 
    89  * ================================================================ 
    90  *   configure DSP RX double buffering state machine (dsp -> eth) 
    91  * ================================================================ 
    92  */ 
    93  
    94 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0) 
    95 // DSP Rx writes timestamp followed by nlines_per_frame of samples 
    96 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1) 
    97  
    98 // receive from DSP 
     86 * ==================================================================== 
     87 *   configure serdes RX double buffering state machine (serdes -> eth) 
     88 * ==================================================================== 
     89 */ 
     90 
     91// receive from serdes 
    9992buf_cmd_args_t dsp_rx_recv_args = { 
    100   PORT_DSP
    101   DSP_RX_FIRST_LINE
     93  PORT_SERDES
     94  0
    10295  BP_LAST_LINE 
    10396}; 
     
    117110 
    118111 
    119 // variables for streaming mode 
    120  
    121 static bool         streaming_p = false; 
    122 static unsigned int streaming_items_per_frame = 0; 
    123 static int          streaming_frame_count = 0; 
    124 #define FRAMES_PER_CMD  1000 
    125  
    126  
    127112// ---------------------------------------------------------------- 
    128  
    129  
    130 static void 
    131 restart_streaming(void) 
    132 { 
    133   // setup RX DSP regs 
    134   dsp_rx_regs->clear_state = 1;                 // reset 
    135  
    136   streaming_p = true; 
    137   streaming_frame_count = FRAMES_PER_CMD; 
    138  
    139   dsp_rx_regs->rx_command = 
    140     MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, 
    141               streaming_items_per_frame, 
    142               1, 1);                    // set "chain" bit 
    143  
    144   // kick off the state machine 
    145   dbsm_start(&dsp_rx_sm); 
    146  
    147   dsp_rx_regs->rx_time = 0;             // enqueue first of two commands 
    148  
    149   // make sure this one and the rest have the "now" and "chain" bits set. 
    150   dsp_rx_regs->rx_command = 
    151     MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, 
    152               streaming_items_per_frame, 
    153               1, 1);                             
    154  
    155   dsp_rx_regs->rx_time = 0;             // enqueue second command 
    156 } 
    157  
    158 void 
    159 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p) 
    160 { 
    161   host_mac_addr = *host;        // remember who we're sending to 
    162  
    163   /* 
    164    * Construct  ethernet header and word0 and preload into two buffers 
    165    */ 
    166   u2_eth_packet_t       pkt; 
    167   memset(&pkt, 0, sizeof(pkt)); 
    168   pkt.ehdr.dst = *host; 
    169   pkt.ehdr.ethertype = U2_ETHERTYPE; 
    170   u2p_set_word0(&pkt.fixed, 0, 0); 
    171   // DSP RX will fill in timestamp 
    172  
    173   memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt)); 
    174   memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt)); 
    175  
    176  
    177   if (FW_SETS_SEQNO) 
    178     fw_seqno = 0; 
    179  
    180   streaming_items_per_frame = p->items_per_frame; 
    181   restart_streaming(); 
    182 } 
    183  
    184  
    185 void 
    186 stop_rx_cmd(void) 
    187 { 
    188   streaming_p = false; 
    189   dsp_rx_regs->clear_state = 1; // flush cmd queue 
    190   bp_clear_buf(DSP_RX_BUF_0); 
    191   bp_clear_buf(DSP_RX_BUF_1); 
    192 } 
    193  
    194  
    195 static void 
    196 setup_tx() 
    197 { 
    198   dsp_tx_regs->clear_state = 1; 
    199   bp_clear_buf(DSP_TX_BUF_0); 
    200   bp_clear_buf(DSP_TX_BUF_1); 
    201  
    202   int tx_scale = 256; 
    203   int interp = 32; 
    204  
    205   // setup some defaults 
    206  
    207   dsp_tx_regs->freq = 0; 
    208   dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale; 
    209   dsp_tx_regs->interp_rate = interp; 
    210 } 
    211113 
    212114 
     
    220122 * but it should work. 
    221123 */ 
     124 
    222125bool  
    223126fw_sets_seqno_inspector(dbsm_t *sm, int buf_this)       // returns false 
    224127{ 
    225128  uint32_t *p = buffer_ram(buf_this); 
     129  uint32_t last_line = buffer_pool_status->last_line[buf_this] - sm->last_line_adj; 
     130  printf("fw_sets_seqno_inspector: buf_this = %d, last_line = %d\n", 
     131         buf_this, last_line); 
     132 
     133  print_buffer(p, (last_line + 1)); 
     134 
     135#if 0 
     136  uint32_t *p = buffer_ram(buf_this); 
    226137  uint32_t seqno = fw_seqno++; 
    227138 
     
    230141  t = (t & 0xffff00ff) | ((seqno & 0xff) << 8); 
    231142  p[4] = t; 
    232  
    233   // queue up another rx command when required 
    234   if (streaming_p && --streaming_frame_count == 0){ 
    235     streaming_frame_count = FRAMES_PER_CMD; 
    236     dsp_rx_regs->rx_time = 0; 
    237   } 
     143#endif 
    238144 
    239145  return false;         // we didn't handle the packet 
     
    247153  uint32_t  status = buffer_pool_status->status; 
    248154 
     155  if (status & ~BPS_IDLE_ALL){ 
     156    putstr("status = "); 
     157    puthex32_nl(status); 
     158  } 
     159     
    249160  dbsm_process_status(&dsp_tx_sm, status); 
    250161  dbsm_process_status(&dsp_rx_sm, status); 
     
    256167  u2_init(); 
    257168 
    258   putstr("\nTxRx\n"); 
     169  putstr("\neth <-> serdes\n"); 
    259170 
    260171  ethernet_register_link_changed_callback(link_changed_callback); 
    261172  ethernet_init(); 
    262173 
     174  clocks_mimo_config(MC_WE_LOCK_TO_SMA | MC_PROVIDE_CLK_TO_MIMO); 
    263175 
    264176#if 0 
     
    268180#endif 
    269181 
     182#if 1 
    270183  output_regs->debug_mux_ctrl = 1; 
    271 #if 0 
    272184  hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); 
    273185  hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); 
     
    277189 
    278190 
    279   // initialize double buffering state machine for ethernet -> DSP Tx 
     191  // initialize double buffering state machine for ethernet -> serdes 
    280192 
    281193  dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, 
     
    284196 
    285197 
    286   // initialize double buffering state machine for DSP RX -> Ethernet 
     198  // initialize double buffering state machine for serdes -> ethernet 
    287199 
    288200  if (FW_SETS_SEQNO){ 
     
    301213 
    302214 
    303   // program tx registers 
    304   setup_tx(); 
    305  
    306215  // kick off the state machine 
    307216  dbsm_start(&dsp_tx_sm); 
    308217 
    309   int which = 0; 
     218  //int which = 0; 
    310219 
    311220  while(1){ 
     
    314223 
    315224    buffer_irq_handler(0); 
    316  
    317     int pending = pic_regs->pending;            // poll for under or overrun 
    318  
    319     if (pending & PIC_UNDERRUN_INT){ 
    320       dbsm_handle_tx_underrun(&dsp_tx_sm); 
    321       pic_regs->pending = PIC_UNDERRUN_INT;     // clear interrupt 
    322       putchar('U'); 
    323     } 
    324  
    325     if (pending & PIC_OVERRUN_INT){ 
    326       dbsm_handle_rx_overrun(&dsp_rx_sm); 
    327       pic_regs->pending = PIC_OVERRUN_INT;      // clear pending interrupt 
    328  
    329       // FIXME Figure out how to handle this robustly. 
    330       // Any buffers that are emptying should be allowed to drain... 
    331  
    332       if (streaming_p){ 
    333         // restart_streaming(); 
    334         // FIXME report error 
    335       } 
    336       else { 
    337         // FIXME report error 
    338       } 
    339       putchar('O'); 
    340     } 
    341225  } 
    342226} 
  • usrp2/trunk/firmware/apps/serdes_txrx.c

    r9145 r9150  
    3333#include "app_common_v2.h" 
    3434#include "memcpy_wa.h" 
     35#include "clocks.h" 
    3536#include <stddef.h> 
    3637#include <stdlib.h> 
     
    4647 
    4748/* 
    48  * Full duplex Tx and Rx between ethernet and DSP pipelines 
     49 * Full duplex Tx and Rx between serdes and DSP pipelines 
    4950 * 
    5051 * Buffer 1 is used by the cpu to send frames to the host. 
    51  * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow 
    52  * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx  eth flow 
     52 * Buffers 2 and 3 are used to double-buffer the DSP Rx to serdes flow 
     53 * Buffers 4 and 5 are used to double-buffer the serdes to DSP Tx flow 
    5354 */ 
    5455//#define CPU_RX_BUF    0       // eth -> cpu 
    5556 
    56 #define DSP_RX_BUF_0    2       // dsp rx -> eth (double buffer) 
    57 #define DSP_RX_BUF_1    3       // dsp rx -> eth 
    58 #define DSP_TX_BUF_0    4       // eth -> dsp tx (double buffer) 
    59 #define DSP_TX_BUF_1    5       // eth -> dsp tx 
    60  
    61 /* 
    62  * ================================================================ 
    63  *   configure DSP TX double buffering state machine (eth -> dsp) 
    64  * ================================================================ 
     57#define DSP_RX_BUF_0    2       // dsp rx -> serdes (double buffer) 
     58#define DSP_RX_BUF_1    3       // dsp rx -> serdes 
     59#define DSP_TX_BUF_0    4       // serdes -> dsp tx (double buffer) 
     60#define DSP_TX_BUF_1    5       // serdes -> dsp tx 
     61 
     62/* 
     63 * ================================================================== 
     64 *   configure DSP TX double buffering state machine (serdes -> dsp) 
     65 * ================================================================== 
    6566 */ 
    6667 
     
    7071#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) 
    7172 
    72 // Receive from ethernet 
     73// Receive from serdes 
    7374buf_cmd_args_t dsp_tx_recv_args = { 
    74   PORT_ETH
     75  PORT_SERDES
    7576  0, 
    7677  BP_LAST_LINE 
     
    8788 
    8889/* 
    89  * ================================================================ 
    90  *   configure DSP RX double buffering state machine (dsp -> eth
    91  * ================================================================ 
     90 * ================================================================= 
     91 *   configure DSP RX double buffering state machine (dsp -> serdes
     92 * ================================================================= 
    9293 */ 
    9394 
     
    103104}; 
    104105 
    105 // send to ETH 
     106// send to serdes 
    106107buf_cmd_args_t dsp_rx_send_args = { 
    107   PORT_ETH
     108  PORT_SERDES
    108109  0,            // starts with ethernet header in line 0 
    109110  0,            // filled in from list_line register 
     
    256257  u2_init(); 
    257258 
    258   putstr("\nTxRx\n"); 
     259  putstr("\nSERDES TxRx\n"); 
     260 
     261  cpu_tx_buf_dest_port = PORT_SERDES; 
    259262 
    260263  ethernet_register_link_changed_callback(link_changed_callback); 
    261264  ethernet_init(); 
    262265 
     266  clocks_mimo_config(MC_WE_LOCK_TO_MIMO); 
    263267 
    264268#if 0 
     
    268272#endif 
    269273 
     274#if 1 
    270275  output_regs->debug_mux_ctrl = 1; 
    271 #if 0 
    272   hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); 
    273   hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); 
     276  hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000"); 
     277  hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000"); 
    274278  hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); 
    275279  hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); 
     
    307311  dbsm_start(&dsp_tx_sm); 
    308312 
    309   int which = 0; 
     313  //int which = 0; 
    310314 
    311315  while(1){ 
  • usrp2/trunk/firmware/apps/txrx.c

    r9090 r9150  
    307307  dbsm_start(&dsp_tx_sm); 
    308308 
    309   int which = 0; 
     309  //int which = 0; 
    310310 
    311311  while(1){ 
  • usrp2/trunk/firmware/lib/Makefile.am

    r8991 r9150  
    4848        print_rmon_regs.c \ 
    4949        print_fxpt.c \ 
     50        print_buffer.c \ 
    5051        printf.c \ 
    5152        spi.c \ 
  • usrp2/trunk/firmware/lib/nonstdio.h

    r8365 r9150  
    2222#include <stdio.h> 
    2323#include <usrp2_types.h> 
     24#include <stddef.h> 
    2425 
    2526void putstr(const char *s);             // cf puts, no added newline 
     
    4142void print_uint64(uint64_t v); 
    4243 
     44void print_buffer(uint32_t *buf, size_t n); 
     45 
    4346#endif /* INCLUDED_NONSTDIO_H */