Changeset 9105

Timestamp:

07/31/08 20:36:46

Author:

matt

Message:

fifo level information for debugging

Files:

• usrp2/trunk/fpga/top/u2_core/u2_core.v (modified) (11 diffs)

usrp2/trunk/fpga/top/u2_core/u2_core.v

@@ -68 +68 @@
-   input cpld_clk,
-   input cpld_detached,
+   //input por,
+   //output config_success,
-   
-   // ADC
@@ -148 +150 @@
-   wire [31:0]  debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, 
-                debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+
+   wire [15:0]  ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire         ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire         ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+        
-   // ///////////////////////////////////////////////////////////////////////////////////////////////
-   // Wishbone Single Master INTERCON
@@ -209 +216 @@
-   //////////////////////////////////////////////////////////////////////////////////////////
-   // Reset Controller
-
+ // .por_i(por),
-                           .ram_loader_rst_o(ram_loader_rst),
-                           .wb_rst_o(wb_rst),
-                           .ram_loader_done_i(ram_loader_done));
+
+   //assign      config_success = ram_loader_done;
-   
-   // ///////////////////////////////////////////////////////////////////
@@ -423 +432 @@
-        .Crs(GMII_CRS),.Col(GMII_COL),
-        .Mdio(MDIO),.Mdc(MDC),
+        .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
+        .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
-        .debug0(debug_mac0),.debug1(debug_mac1) );
-
@@ -434 +445 @@
-      .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
-      .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
-
+
+
-
-   mac_txfifo_int mac_txfifo_int
@@ -441 +453 @@
-      .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
-      .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
-
-
+
+
+
-   // /////////////////////////////////////////////////////////////////////////
-   // Interrupt Controller, Slave #8
@@ -522 +535 @@
-      .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
-      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
-      .debug_rx(debug_rx) );
-   
@@ -539 +553 @@
-      .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
-      .debug(debug_txc) );
-   
@@ -560 +575 @@
-      .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
-      .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
-      .debug0(debug_serdes0), .debug1(debug_serdes1) );
-
@@ -579 +596 @@
-   // Debug Pins
-
+   // FIFO Level Debugging
+   reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug;
+
+   always @(posedge dsp_clk)
+     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+                           {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+                          {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     eth_mac_debug <= {
+                      // {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]},
+                      // {underrun, overrun, debug_mac0[13:0] },
+                       {debug_txc[15:0]},
+                       {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+   
+   wire       debug_mux;
+   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                        .in(set_data),.out(debug_mux),.changed());
+
+   assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+   
-   // Assign various commonly used debug buses.
-   /*
@@ -626 +667 @@
-   assign      debug_clk[1] = dsp_clk;  
-   
-
-
+//
+//
-
-   //assign      debug = debug_tx_dsp;
-
-//assign      debug = 0; // debug_serdes0;
+//assign      debug = debug_serdes0;
+
-   assign      debug_gpio_0 = 0; // debug_serdes1;
-32'b0
+eth_mac_debug
-   
-endmodule // u2_core