Changeset 9100
- Timestamp:
- 07/31/08 20:29:50
- Files:
-
- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v (modified) (2 diffs)
- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v (modified) (4 diffs)
Legend:
- Unmodified
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usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v
r7578 r9100 96 96 output [2:0] Rx_pkt_err_type_rmon , 97 97 output [2:0] Rx_pkt_type_rmon , 98 99 output [15:0] rx_fifo_occupied, 100 output rx_fifo_full, 101 output rx_fifo_empty, 98 102 output [31:0] debug 99 103 ); … … 192 196 .Rx_mac_sop (Rx_mac_sop ), 193 197 .Rx_mac_eop (Rx_mac_eop ), 194 .Rx_mac_err (Rx_mac_err ) 198 .Rx_mac_err (Rx_mac_err ), 199 200 .fifo_occupied(rx_fifo_occupied), 201 .fifo_full_dbg(rx_fifo_full), 202 .fifo_empty(rx_fifo_empty) 195 203 ); 196 204 usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
r8890 r9100 17 17 input Fifo_data_end, 18 18 output [15:0] Fifo_space, 19 19 20 20 // CPU 21 21 input RX_APPEND_CRC, … … 30 30 output Rx_mac_sop, 31 31 output Rx_mac_eop, 32 output Rx_mac_err 32 output Rx_mac_err, 33 34 // FIFO Levels 35 output [15:0] fifo_occupied, 36 output fifo_full_dbg, 37 output fifo_empty 33 38 ); 34 39 … … 115 120 wire sop_o, eop_o, empty; 116 121 wire [1:0] be_o; 117 wire [RX_FF_DEPTH-1:0] occupied ;122 wire [RX_FF_DEPTH-1:0] occupied, occupied_sysclk; 118 123 wire [31:0] dataout; 119 124 … … 138 143 .empty(empty), 139 144 .full(Fifo_full), 140 .rd_data_count( ), // Bus [11 : 0]145 .rd_data_count(occupied_sysclk), // Bus [11 : 0] 141 146 .wr_data_count(occupied)); // Bus [11 : 0] 142 147 143 148 assign Fifo_space[15:RX_FF_DEPTH] = 0; 144 149 assign Fifo_space[RX_FF_DEPTH-1:0] = ~occupied; 145 150 assign fifo_occupied = occupied_sysclk; 151 assign fifo_full_dbg = Fifo_full; // FIXME -- in wrong clock domain 152 assign fifo_empty = empty; 153 146 154 // mac side fifo interface 147 155 // Input - Rx_mac_rd
