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Changeset 9098

Timestamp:

07/31/08 20:26:42

Author:

matt

Message:

pass fifo information to the outside

Files:

r8894	r9098
17	17	output rd_error_o,
18	18	input rd_sop_i,
19		input rd_eop_i);
	19	input rd_eop_i,
	20
	21	// FIFO Status
	22	output [15:0] fifo_occupied,
	23	output fifo_full,
	24	output fifo_empty );
20	25
21	26	wire empty, full, sfifo_write, sfifo_read;
…	…
30	35	fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
31	36	(.rst(rst),
32		.wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),
33		.rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read));
	37	.wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),.wr_data_count(fifo_occupied[8:0]),
	38	.rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read),.rd_data_count() );
	39	assign fifo_occupied[15:9] = 0;
	40	assign fifo_full = full;
	41	assign fifo_empty = empty; // Note empty is in wrong clock domain
34	42
35	43	// MAC side signals
…	…
68	76
69	77	endmodule // mac_txfifo_int
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