Changeset 9096

Timestamp:

07/31/08 20:21:43

Author:

matt

Message:

fixed major bug in xfer_state state machine which would cause it to refill with junk when there was an underflow.
Also added fifo level outputs and adapted to the new interface for the fifo full/empty connections.

Files:

• usrp2/trunk/fpga/sdr_lib/tx_control.v (modified) (4 diffs)

usrp2/trunk/fpga/sdr_lib/tx_control.v

@@ -23 +23 @@
-     input strobe,
-
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full,
+     output fifo_empty,
+
+     // Debug
-     output [31:0] debug
-     );
@@ -41 +47 @@
-     if(rst)
-       xfer_state <= XFER_IDLE;
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-   
-   assign write_data = (xfer_state == XFER_DATA) & ~full_data;
@@ -69 +78 @@
-   wire        sop_o, eop_o, eob, sob, send_imm;
-   wire [31:0] sendtime;
+   wire [4:0]  occ_ctrl;
-   
-   cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) txctrlfifo
-     (.clk(clk),.rst(rst),.clear(clear_state),
-      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), .full(full_data),
-
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-   shortfifo #(.WIDTH(35)) ctrlfifo
-     (.clk(clk),.rst(rst),.clear(clear_state),
-      .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), .full(full_ctrl),
-
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-
-   // Internal FIFO to DSP interface
@@ -140 +154 @@
-   assign      sample = data_o;
-
-16'd0
-eop_o, eob, send_imm ,too_late, go_now, ibs_state[2:0] }, 
-empty_data, empty_ctrl, read_data, read_ctrl, strobe, clear_state, run, underrun
+{16'b0}
+ read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl },
+{ occ_ctrl, eop_o, clear_state, underrun} 
-   
-endmodule // tx_control