Changeset Navigation

Changeset 9093

Timestamp:

07/31/08 20:18:26

Author:

matt

Message:

Fixed major bug in determining when the fifo is full. The problem was with bit vectors being expanded quietly and signed math creeping in.

Files:

r7198	r9093
16	16	output full,
17	17	output empty,
18		output [15:0] fifo_space);
	18	output [15:0] space,
	19	output [15:0] occupied);
19	20
20	21	// Read side states
…	…
27	28
28	29	wire [SIZE-1:0] fullness = wr_addr - rd_addr; // Approximate, for simulation only
	30	assign occupied = {{16-SIZE{1'b0}},fullness};
	31
29	32	wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2; // Approximate, for SERDES flow control
	33	assign space = {{16-SIZE{1'b0}},free_space};
	34
30	35	reg empty_reg, full_reg;
31		~~assign fifo_space = {{16-SIZE{1'b0}},free_space};~~
32
33	36	always @(posedge clk)
34	37	if(rst)
…	…
96	99	rd_addr <= rd_addr + 1;
97	100	endcase // case(read_state)
98
	101
	102	wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
	103	wire becoming_full = wr_addr == dont_write_past_me;
	104
99	105	always @(posedge clk)
100	106	if(rst)
…	…
104	110	else if(read & ~write)
105	111	full_reg <= 0;
106		else if(write & ~read & (wr_addr == (rd_addr-3)))
	112	//else if(write & ~read & (wr_addr == (rd_addr-3)))
	113	else if(write & ~read & becoming_full)
107	114	full_reg <= 1;
108	115