Changeset 9092
- Timestamp:
- 07/31/08 20:16:11
- Files:
-
- usrp2/trunk/fpga/control_lib/medfifo.v (modified) (4 diffs)
- usrp2/trunk/fpga/control_lib/simple_uart_rx.v (modified) (1 diff)
- usrp2/trunk/fpga/control_lib/simple_uart_tx.v (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
usrp2/trunk/fpga/control_lib/medfifo.v
r8730 r9092 11 11 output full, 12 12 output empty, 13 output [ 3:0] space,14 output [ 3:0] occupied);13 output [7:0] space, 14 output [7:0] occupied); 15 15 16 16 localparam NUM_FIFOS = (1<<DEPTH); … … 24 24 .datain(datain),.write(write),.full(full), 25 25 .dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]), 26 .clear(clear),.space(space ),.occupied() );26 .clear(clear),.space(space[4:0]),.occupied() ); 27 27 28 28 shortfifo #(.WIDTH(WIDTH)) … … 30 30 .datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & ~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]), 31 31 .dataout(dataout),.read(read),.empty(empty), 32 .clear(clear),.space(),.occupied(occupied ) );32 .clear(clear),.space(),.occupied(occupied[4:0]) ); 33 33 34 34 genvar i; … … 44 44 endgenerate 45 45 46 assign space[7:5] = 0; 47 assign occupied[7:5] = 0; 48 46 49 endmodule // medfifo usrp2/trunk/fpga/control_lib/simple_uart_rx.v
r8726 r9092 60 60 .datain(sr),.write(write),.full(full), 61 61 .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), 62 .clear(0),.space(),.occupied(fifo_level[3:0]) ); 63 assign fifo_level[7:4] = 0; 62 .clear(0),.space(),.occupied(fifo_level) ); 64 63 65 64 endmodule // simple_uart_rx usrp2/trunk/fpga/control_lib/simple_uart_tx.v
r8719 r9092 16 16 .datain(fifo_in),.write(fifo_write),.full(fifo_full), 17 17 .dataout(char_to_send),.read(read),.empty(empty), 18 .clear(0),.space(fifo_level[3:0]),.occupied() ); 19 assign fifo_level[7:4] = 0; 18 .clear(0),.space(fifo_level),.occupied() ); 20 19 21 20 always @(posedge clk)
