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Changeset 8987

Timestamp:

07/23/08 17:45:22

Author:

gnychis

Message:

work in progress on a single clock as input to both TX and RX modules, rather than two clocks reset at the same time

Files:

r8430	r8987
114	114	reg [15:0] debug_counter;
115	115	reg [15:0] loopback_i_0,loopback_q_0;
116
	116
	117	// Single timestamp clock for both TX and RX
	118	reg [31:0] timestamp_clock;
	119	always @(posedge clk64) // reset the timestamp clock on TX DSP reset
	120	if(tx_dsp_reset)
	121	timestamp_clock <= #1 32'd0;
117	122
118	123	//Connection RX inband <-> TX inband