Changeset 8927

Timestamp:

07/17/08 15:07:52

Author:

matt

Message:

run the watchdog timer on the rev3

Files:

• usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v (modified) (2 diffs)

usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v

@@ -156 +156 @@
-   );
-
-   assign       WDI = 0;
-   
-   assign       cpld_init_b = 0;
-   // FPGA-specific pins connections
@@ -163 +161 @@
-   wire         clk90, clk180, clk270;
-
+   // reset the watchdog continuously
+   reg [15:0]   wd;
+   always @(posedge wb_clk)
+     if(POR)
+       wd <= 0;
+     else
+       wd <= wd + 1;
+   assign       WDI = wd[15];
+   
-   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
-   defparam     clk_fpga_pin.IOSTANDARD = "LVPECL_25";