Changeset 8331

Timestamp:

05/08/08 19:46:26

Author:

matt

Message:

rearranged atr and debug lines

Files:

• usrp2/trunk/fpga/top/u2_core/u2_core.v (modified) (3 diffs)

usrp2/trunk/fpga/top/u2_core/u2_core.v

@@ -343 +343 @@
-                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
-                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-
-
+
-                 .gpio( {io_tx,io_rx} ) );
-   assign        s4_err = 1'b0;
@@ -620 +619 @@
-                                 { ser_r[15:8] },
-                                 { ser_r[7:0] } };
-
+
-   wire [31:0] debug_serdes_receiver = {uart_tx_o,debug_serdes2[30:0]};
-   wire [31:0] debug_serdes_sender = { uart_tx_o, debug_serdes0[30:0]};
-   wire [31:0] debug_serdes_common = debug_serdes1;
-   
-   /*
-   assign      debug_gpio_1 = {uart_tx_o,7'd0,
-                               3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
@@ -640 +638 @@
-   
-   assign      debug = debug_serdes0; //_common;
-//assign      debug_gpio_0 = debug_serdes_sender
-{uart_tx_o, debug_serdes1[30:0]}
+assign      debug_gpio_0 = 32'b0
+debug_serdes1[31:0]
-   
-endmodule // u2_core