Changeset 8330
- Timestamp:
- 05/08/08 19:45:48
- Files:
-
- usrp2/trunk/fpga/control_lib/atr_controller.v (modified) (1 diff)
- usrp2/trunk/fpga/control_lib/nsgpio.v (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
usrp2/trunk/fpga/control_lib/atr_controller.v
r6992 r8330 8 8 input [3:0] adr_i, input [31:0] dat_i, output [31:0] dat_o, 9 9 input we_i, input stb_i, input cyc_i, output reg ack_o, 10 input run_rx, input run_tx, output [31:0] ctrl_lines); 10 input run_rx, input run_tx, input [31:0] master_time, 11 output [31:0] ctrl_lines); 11 12 12 13 reg [3:0] state; usrp2/trunk/fpga/control_lib/nsgpio.v
r6867 r8330 1 // Modified from code originally by Richard Herveille, his copyright is below 2 1 3 ///////////////////////////////////////////////////////////////////// 2 4 //// //// … … 38 40 input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, 39 41 output reg [31:0] dat_o, output reg ack_o, 40 input [31:0] debug_0, input [31:0] debug_1, inout [31:0] gpio 42 input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 43 inout [31:0] gpio 41 44 ); 42 45 … … 44 47 reg [31:0] line; 45 48 reg [31:0] lgpio; // LatchedGPIO pins 49 reg [31:0] ddr; 46 50 47 51 wire wb_acc = cyc_i & stb_i; // WISHBONE access … … 62 66 2'b10 : 63 67 ctrl[63:32] <= dat_i; 68 2'b11 : 69 ddr[31:0] <= dat_i; 64 70 endcase // case( adr_i[3:2] ) 65 71 … … 72 78 2'b10 : 73 79 dat_o <= ctrl[63:32]; 80 2'b11 : 81 dat_o <= ddr; 74 82 endcase // case(adr_i[3:2]) 75 83 … … 88 96 reg [31:0] igpio; // temporary internal signal 89 97 90 always @(ctrl or line or debug_1 or debug_0 )98 always @(ctrl or line or debug_1 or debug_0 or atr) 91 99 for(n=0;n<32;n=n+1) 92 igpio[n] <= ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 93 (ctrl[2*n] ? line[n] : 1'bz); 100 igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 101 (ctrl[2*n] ? atr[n] : line[n]) ) 102 : 1'bz; 94 103 95 104 assign gpio = igpio;
