Changeset 8268

Timestamp:

04/24/08 11:44:37

Author:

matt

Message:

don't connect uart rx due to timing problems

Files:

• usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise (modified) (previous)
• usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj (modified) (1 diff)
• usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v (modified) (1 diff)

usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj

@@ -6 +6 @@
-verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
-verilog work "../../control_lib/shortfifo.v"
-verilog work "../../control_lib/longfifo.v"

usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v

@@ -386 +386 @@
-                     .RAM_LDn           (RAM_LDn), 
-                     .uart_tx_o         (uart_tx_o),
-
+  the rx side causes timing problems
-                     .uart_rx_i         (),
-                     .uart_baud_o       (),