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Changeset 8002

Timestamp:

03/12/08 13:14:48

Author:

matt

Message:

proper reference locking

Files:

r7998	r8002
31	31	#include <stdlib.h>
32	32	#include <string.h>
	33	#include <ad9510.h>
33	34
34	35	// ----------------------------------------------------------------
…	…
97	98	{
98	99	u2_init();
	100
	101	// Get our clock from the mimo interface
	102
	103	// if(I WANT TO LOCK TO A REFERENCE CLOCK)
	104	// Reg 8, Charge pump on, dig lock det, positive PFD, 47
	105	ad9510_write_reg(0x08, 0x47);
	106	ad9510_write_reg(0x5A, 0x01); // Update Regs
	107	// if (LOCK_TO_MIMO_REF)
	108
	109	// Turn on ref output and choose the MIMO connector
	110	output_regs->clk_ctrl = 0x15;
	111	// Turn on ref output and choose the SMA connector
	112	//output_regs->clk_ctrl = 0x14;
99	113
100	114	// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output

r7982	r8002
31	31	#include <stdlib.h>
32	32	#include <string.h>
	33	#include <ad9510.h>
33	34
34	35	// ----------------------------------------------------------------
…	…
97	98	{
98	99	u2_init();
	100
	101
	102	// Reg 8, Charge pump on, dig lock det, positive PFD, 47
	103	ad9510_write_reg(0x08, 0x47);
	104	// turn on ref input and choose the SMA
	105	output_regs->clk_ctrl = 0x14;
	106
	107	// provide a clock for the serdes (THEY_LOCK_TO_ME)
	108	ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal levels
	109	ad9510_write_reg(0x4D, 0x00); // Turn on Div2
	110	ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock
	111	ad9510_write_reg(0x5A, 0x01); // Update Regs
	112
	113
99	114
100	115	// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output