Changeset 7818

Timestamp:

02/24/08 12:08:20

Author:

matt

Message:

register the serdes outputs in the iobuffer flops

Files:

• usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v (modified) (4 diffs)

usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v

@@ -58 +58 @@
-   
-   output ser_tx_clk,
-
-
-
+reg 
+reg 
+reg 
-
-   input ser_rx_clk,
@@ -252 +252 @@
-     end
-
-
+gmii_
-     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
-      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
@@ -263 +263 @@
-      );
-   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+        ser_tklsb <= ser_tklsb_unreg;
+        ser_tkmsb <= ser_tkmsb_unreg;
+        ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
-   u2_basic u2_basic(.dsp_clk           (dsp_clk),
-                     .wb_clk            (wb_clk),
@@ -294 +319 @@
-                     .ser_loopen        (ser_loopen),
-                     .ser_rx_en         (ser_rx_en),
-
-
-
-
+_int
+_unreg
+_unreg
+_unreg
-                     .ser_rx_clk        (ser_rx_clk),
-                     .ser_r             (ser_r[15:0]),