Changeset 7816
- Timestamp:
- 02/24/08 12:06:59
- Files:
-
- usrp2/trunk/fpga/serdes/serdes_rx.v (modified) (4 diffs)
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usrp2/trunk/fpga/serdes/serdes_rx.v
r7175 r7816 40 40 41 41 output [15:0] fifo_space, 42 output xon_rcvd, output xoff_rcvd 42 output xon_rcvd, output xoff_rcvd, 43 output [31:0] debug 43 44 ); 44 45 … … 205 206 if(chosen_data[17:0] == {2'b00,CRC}) 206 207 begin 207 state <= DONE; 208 eop_i <= 1; 208 if(full) 209 state <= ERROR; 210 else 211 begin 212 eop_i <= 1; 213 state <= DONE; 214 end 209 215 end 210 216 else if(wait_here) … … 256 262 if(rst) 257 263 xfer_active <= 0; 258 else if( ~empty & (eop_o | wr_full_i))264 else if(xfer_active & ~empty & (eop_o | wr_full_i | error_o)) 259 265 xfer_active <= 0; 260 266 else if(wr_ready_i & sop_o) … … 266 272 assign wr_done_o = eop_o & ~empty & xfer_active; 267 273 //assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o & ~empty)|error_o); 268 assign wr_error_o = xfer_active & error_o;274 assign wr_error_o = xfer_active & ~empty & error_o; 269 275 270 276 assign wr_dat_o = line_o; 277 278 assign debug = { { fifo_space[15:8] }, 279 { fifo_space[7:0] }, 280 { 2'd0, error_i, sop_i, eop_i, error_o, sop_o, eop_o }, 281 { full, empty, write, read, xfer_active, state[2:0] } }; 271 282 272 283 endmodule // serdes_rx
