Changeset 7486
- Timestamp:
- 01/21/08 17:06:28
- Files:
-
- gnuradio/trunk/gr-usrp/src/db_flexrf.py (modified) (2 diffs)
Legend:
- Unmodified
- Added
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gnuradio/trunk/gr-usrp/src/db_flexrf.py
r7484 r7486 89 89 #print "flexrf_base.__del__" 90 90 self._u.write_io(self._which, self.power_off, POWER_UP) # turn off power to board 91 # Power down VCO/PLL 92 self.PD = 3 93 self._write_control(self._compute_control_reg()) 91 94 self._enable_refclk(False) # turn off refclk 92 95 self.set_auto_tr(False) … … 411 414 | (self.ABP<<16) | (self.R_DIV<<2) 412 415 416 control = self._compute_control_reg() 417 418 N = (self.DIVSEL<<23) | (self.DIV2<<22) | (self.CPGAIN<<21) | (self.B_DIV<<8) | \ 419 (self.N_RSV<<7) | (self.A_DIV<<2) 420 421 return (R,control,N,actual_freq/self.freq_mult) 422 423 def _compute_control_reg(self): 413 424 control = (self.P<<22) | (self.PD<<20) | (self.CP2<<17) | (self.CP1<<14) | (self.PL<<12) \ 414 425 | (self.MTLD<<11) | (self.CPG<<10) | (self.CP3S<<9) | (self.PDP<<8) | \ 415 426 (self.MUXOUT<<5) | (self.CR<<4) | (self.PC<<2) 416 417 N = (self.DIVSEL<<23) | (self.DIV2<<22) | (self.CPGAIN<<21) | (self.B_DIV<<8) | \ 418 (self.N_RSV<<7) | (self.A_DIV<<2) 419 420 return (R,control,N,actual_freq/self.freq_mult) 427 return control 421 428 422 429 def _refclk_divisor(self):
