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Changeset 6064

Timestamp:

07/25/07 11:01:29

Author:

matt

Message:

first code drop from Claus on July 24th 2007
changed case on some filenames, added vcd generation

Files:

r6058	r6064
16	16	output empty);
17	17
	18	// Read side states
	19	localparam EMPTY = 0;
	20	localparam PRE_READ = 1;
	21	localparam READING = 2;
	22
18	23	reg [SIZE-1:0] wr_addr, rd_addr;
19	24	reg [1:0] read_state;
20	25
21	26	wire [SIZE-1:0] fullness = wr_addr - rd_addr; // For simulation only
	27
	28	reg empty_reg, full_reg;
22	29
23	30	always @(posedge clk)
…	…
26	33	else if(write)
27	34	wr_addr <= wr_addr + 1;
28
29		~~// Read side states~~
30		~~localparam EMPTY = 0;~~
31		~~localparam PRE_READ = 1;~~
32		~~localparam READING = 2;~~
33	35
34	36	ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
…	…
52	54	read_state <= EMPTY;
53	55	rd_addr <= 0;
	56	empty_reg <= 1;
54	57	end
55	58	else
…	…
64	67	begin
65	68	read_state <= READING;
	69	empty_reg <= 0;
66	70	rd_addr <= rd_addr + 1;
67	71	end
…	…
71	75	begin
72	76	if(rd_addr == wr_addr)
73		read_state <= EMPTY;
	77	begin
	78	read_state <= EMPTY;
	79	empty_reg <= 1;
	80	end
74	81	else
75	82	rd_addr <= rd_addr + 1;
…	…
77	84	endcase // case(read_state)
78	85
79		assign empty = (read_state != READING);
80		assign full = ((rd_addr - 1) == wr_addr);
81
	86	always @(posedge clk)
	87	if(rst)
	88	full_reg <= 0;
	89	else if(read & ~write)
	90	full_reg <= 0;
	91	else if(write & ~read & (wr_addr == (rd_addr-2)))
	92	full_reg <= 1;
	93
	94	/* always @(posedge clk)
	95	if(rst)
	96	empty_reg <= 1;
	97	else if(write & ~read)
	98	empty_reg <= 0;
	99	else if(read & ~write & (wr_addr == (rd_addr+1)))
	100	empty_reg <= 1;
	101	*/
	102
	103	//assign empty = (read_state != READING);
	104	assign empty = empty_reg;
	105
	106	// assign full = ((rd_addr - 1) == wr_addr);
	107	assign full = full_reg;
	108
82	109	endmodule // longfifo

r5920	r6064
65	65
66	66	reg [15:0] second_word;
67
	67	reg [33:0] pipeline;
	68
	69	always @(posedge clk)
	70	if(rst)
	71	pipeline <= 34'd0;
	72	else
	73	pipeline <= {fifo_ready_i, fifo_empty_i, fifo_data_i};
	74	wire fifo_ready_d = pipeline[33];
	75	wire fifo_empty_d = pipeline[32];
	76	wire [31:0] fifo_data_d = pipeline[31:0];
	77
68	78	always @(posedge clk)
69	79	if(rst)
…	…
77	87	begin
78	88	{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
79		if(fifo_ready_i)
	89	if(fifo_ready_d)
80	90	state <= START;
81	91	end
…	…
87	97	RUN1 :
88	98	begin
89		{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_i[15:0]};
	99	{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_d[15:0]};
90	100	state <= RUN2;
91		second_word <= fifo_data_i[31:16];
	101	second_word <= fifo_data_d[31:16];
92	102	end
93	103	RUN2 :
…	…
96	106	if(fifo_empty_i)
97	107	state <= DONE;
98		else if(fifo_ready_i)
	108	else if(fifo_ready_d)
99	109	state <= RUN1;
100	110	else
…	…
104	114	begin
105	115	{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
106		if(fifo_ready_i)
	116	if(fifo_ready_d)
107	117	state <= RUN1;
108	118	end

r6036	r6064
18	18	void int_handler_func () __attribute__ ((interrupt_handler));
19	19
20		~~void int_handler_func () {}~~
21	20	void double_buffering();
	21
	22	void int_handler_func () {
	23	double_buffering();
	24	}
22	25
23	26	int
…	…
38	41	dsp_tx_regs->scale_i = 1;
39	42	dsp_tx_regs->scale_q = 1;
40		dsp_tx_regs->interp_rate = 32;
	43	dsp_tx_regs->interp_rate = 7;
41	44
42	45	// Set up RX Chain
…	…
44	47	dsp_rx_regs->scale_i = 1;
45	48	dsp_rx_regs->scale_q = 1;
46		dsp_rx_regs->decim_rate = 32;
	49	dsp_rx_regs->decim_rate = 7;
47	50
48	51	// Set up buffer control, using only 4 for now
…	…
63	66	receive_to_buf(2, 0, 1, 5, 504);
64	67
	68	sim_puts("Done DSP TX setup\n");
	69	sim_puts("Done DSP TX setup\n");
65	70	dsp_tx_regs->run_tx = 1;
66		sim_puts("Done DSP TX setup\n");
67
68		while(1) {
69		double_buffering();
70		}
	71
	72	while(1) {}
	73	//double_buffering();
	74	//}
71	75
72	76	sim_finish();

r5937	r6064
9	9	verilog work "../../opencores/aemb/rtl/verilog/aeMB_control.v"
10	10	verilog work "../../opencores/aemb/rtl/verilog/aeMB_aslu.v"
	11	verilog work "../../control_lib/ram_2port.v"
11	12	verilog work "../../sdr_lib/cordic.v"
12	13	verilog work "../../sdr_lib/cic_interp.v"
…	…
18	19	verilog work "../../control_lib/strobe_gen.v"
19	20	verilog work "../../control_lib/ss_rcvr.v"
20		~~verilog work "../../control_lib/shortfifo.v"~~
21	21	verilog work "../../control_lib/setting_reg.v"
22		~~verilog work "../../control_lib/ram_2port.v"~~
23	22	verilog work "../../control_lib/mux8.v"
24	23	verilog work "../../control_lib/mux4.v"
	24	verilog work "../../control_lib/longfifo.v"
25	25	verilog work "../../control_lib/fifo_int.v"
26	26	verilog work "../../control_lib/decoder_3_8.v"
…	…
32	32	verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
33	33	verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
	34	verilog work "../../control_lib/wb_readback_mux.v"
34	35	verilog work "../../control_lib/wb_1master.v"
35	36	verilog work "../../control_lib/system_control.v"